ADIN1300CCPZ-R7 datasheet(75/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 75 of 79

Bits

Bit Name

Description

Reset

Access

GE_RMII_TXD_CHK_EN

This bit determines whether or not the TXD_0 pin and TXD_1 pin are

monitored to detect the start of a frame. This bit allows connecting the RMII

receive CRS_DV to the RMII TX_EN signal. This allows a receive to transmit RMII

pin loopback for media converter applications. This is something that it is not

supported in the RMII specification.

0x0

R/W

GE_RMII_CRS_EN

This bit determines whether or not CRS is encoded in the CRS_DV output

signal. This allows a receive to transmit RMII pin loopback for media converter

applications. This is something that it is not supported in the RMII specification.

0x1

R/W

GE_RMII_BAD_SSD_RX_ER_EN

This bit determines whether or not the RX_ER output signal is asserted when

a false carrier (bad SSD) is detected. When cleared, RX_ER is only asserted in

case of a symbol error during a frame.

0x1

R/W

GE_RMII_EN

This bit selects the RMII MAC interface mode. Note that the default value of

this register bit is configurable via hardware configuration pins. This allows

the default operation of the PHY to be configured in unmanaged applications.

As RMII mode requires a 50 MHz reference clock, the RMII interface must be

configured from the hardware configuration pins and not from software.

0x0

R/W

Subsystem PHY Base Configuration Register

Address: 0xFF26, Reset: 0x0C86, Name: GE_PHY_BASE_CFG

This subsystem register allows the enhanced link detection function of the PHY to be configured for 100BASE-TX and for 1000BASE-T,

and allows 1000BASE-T retrain to be configured. Each time a PHY core software reset is issued, the PHY resets its registers, including the

1000BASE-T retrain enable register bit (B_1000_RTRN_EN bit, Address 0x1E.0xA001, Bit 0) and the enhanced link detection 1000BASE-T and

100BASE-TX enable register bits (within the FLD_EN register, Address 0x1E.0x8E27). The default value of the B_1000_RTRN_EN bit is

set via the 1000BASE-T retrain enable configuration bit (GE_RTRN_EN_CFG, within this register). The default value of the enhanced

link detection 1000BASE-T enable register bits (within the FLD_EN register) are set via the GE_FLD_1000_EN_CFG bit and

GE_FLD_100_EN_CFG bit within this register. If the value of any of these enable configuration bits are changed, the corresponding

1000BASE-T retrain enable register bit and the enhanced link detection 1000BASE-T and 100BASE-TX enable register bits in the PHY

only change after a PHY software reset.

Table 121. Bit Descriptions for GE_PHY_BASE_CFG

Bits

Bit Name

Description

Reset

Access

[15:13]

RESERVED

Reserved.

0x0

GE_RTRN_EN_CFG

When this bit is set, the IEEE Standard 802.3 1000BASE-T retrain functionality is

enabled in the PHY.

0x0

R/W

GE_FLD_1000_EN_CFG

When this bit is set, the enhanced link detection functionality is enabled when the

PHY establishes a 1000BASE-T link.

0x1

R/W

GE_FLD_100_EN_CFG

When this bit is set, the enhanced link detection functionality is enabled when the

PHY establishes a 100BASE-TX link.

0x1

R/W

[9:4]

RESERVED

Reserved.

0x8

R/W

GE_PHY_SFT_PD_CFG

When this bit is set, the PHY enters software power-down on exit from reset.

0x0

R/W

[2:0]

RESERVED

Reserved.

0x6

R/W

Subsystem Link Status Invert Enable Register

Address: 0xFF3C, Reset: 0x0000, Name: GE_LNK_STAT_INV_EN

This register allows the link status output signal on the LINK_ST pin to be inverted, meaning that link up is indicated by setting LINK_ST

low.

Table 122. Bit Descriptions for GE_LNK_STAT_INV_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

GE_LNK_STAT_INV_EN

When set to 1, this bit enables the link status output signal on the LINK_ST pin to be

inverted, meaning that link up is indicated by setting LINK_ST low.

0x0

R/W

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