ADIN1300CCPZ-R7 datasheet(54/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 54 of 79

Bits

Bit Name

Description

Reset

Access

[7:4]

LED_PAT_PAUSE_DUR

Internal LED Pattern Pause Duration for LED_0. After the blink pattern is driven out

to the LED_0 pin, the last bit is held for a duration specified by the LED pattern pause

duration register field. This duration is the value of LED tick duration (for example,

the time for each bit) multiplied by the value of the LED pattern pause duration register

field. Also see the LED_PAT register field (LED_CTRL_3 register, Address 0x001D,

Bits[7:0]) and the LED_PAT_TICK_DUR register field (LED_CTRL_3 register,

Address 0x001D, Bits[13:8]). The default blink is a 0.5 sec on and 0.5 sec off pattern.

0x0

R/W

[3:2]

LED_PUL_STR_DUR_SEL

This bit field selects the duration of the pulse stretching.

0x0

R/W

11: user-programmable. In this case, the duration of the pulse stretching is

programmable by the LED_PUL_STR_DUR register (Address 0xBC00, Bits[5:0]).

10: 102 ms.

01: 64 ms.

00: 32 ms.

LED_OE_N

LED Active Low Output Enable Register Bit.

0x0

R/W

1: disable LED outputs.

0: enable LED outputs.

LED_PUL_STR_EN

Setting this bit enables pulse stretching for transmit, receive, or collision LED events

so that very short duration events are visible. The LED pulse stretching enable register

indicates that the PHY must stretch any pulses indicating transmit, receive, or

collision. Without stretching, these pulses may be too short to cause an LED to light.

0x1

R/W

LED Control 2 Register

Address: 0x001C, Reset: 0x210A, Name: LED_CTRL_2

This register provides access to various PHY LED control register bits.

Table 55. Bit Descriptions for LED_CTRL_2

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x210

R/W

[3:0]

LED_A_CFG

LED_0 configuration is made up of five bits. These four bits, Bits[3:0], are the LSBs and Bit 4 is

from LED_A_EXT_CFG_EN (LED_CTRL_1 register, Address 0x001B). The combination of the five bits

configures LED_0, selecting one of 32 possible configuration functions according to the

following settings. The default setting is 01010 (on if link up and blink on activity).

0xA

R/W

11111: on if 10BASE-T link, blink if 100BASE-TX link.

11110: on if 10BASE-T link, blink if 1000BASE-T link.

11101: on if 100BASE-TX link, blink if 10BASE-T link.

11100: on if 100BASE-TX link, blink if 1000BASE-T link.

11011: on if 1000BASE-T link, blink if 10BASE-T link.

11010: blink if transmit.

11001: blink on activity.

11000: on if 10BASE-T or 1000BASE-T link, blink on activity.

10111: on if 10BASE-T or 1000BASE-T link.

10110: on if 100BASE-TX or 1000BASE-T link, blink on activity.

10101: on if 10BASE-T or 100BASE-TX link, blink on activity.

10100: on if 1000BASE-T link, blink on activity.

10011: on if 100BASE-TX link, blink on activity.

10010: on if 10BASE-T link, blink on activity.

10001: on if 100BASE-TX or 1000BASE-T link.

10000: on if 10BASE-T or 100BASE-TX link.

01111: off.

01110: on.

01101: blink.

01100: on if full duplex link, blink on collision.

01011: on if link, blink if receiving.

01010: on if link, blink on activity (default).

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