ADIN1300CCPZ-R7 datasheet(63/79 Pages) AD

63 / 79 page

Data Sheet

ADIN1300

Rev. 0 | Page 63 of 79

Frame Checker Dribble Bits Frame Count Register

Address: 0x9413, Reset: 0x0000, Name: FC_DRIBBLE_BITS_CNT

This register is a latched copy of the dribble bits frame counter register. This register is a count of received frames with a noninteger

number of nibbles in 10BASE-T mode. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the dribble bits

frame counter register is latched, which ensures that the dribble bits frame count and receive frame count are synchronized.

Table 83. Bit Descriptions for FC_DRIBBLE_BITS_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_DRIBBLE_BITS_CNT

Latched Copy of the Dribble Bits Frame Counter.

0x0

Frame Checker False Carrier Count Register

Address: 0x9414, Reset: 0x0000, Name: FC_FALSE_CARRIER_CNT

This register is a latched copy of the false carrier events counter register. This is a count of the number of times the BAD SSD state is

entered. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the false carrier events counter register is

latched, which ensures that the false carrier events count and receive frame count are synchronized.

Table 84. Bit Descriptions for FC_FALSE_CARRIER_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FALSE_CARRIER_CNT

Latched Copy of the False Carrier Events Counter.

0x0

Frame Generator Enable Register

Address: 0x9415, Reset: 0x0000, Name: FG_EN

This register is used to enable the frame generator. When the frame generator is enabled, the source of data for the PHY comes from the

frame generator and not the MAC interface. To use the frame generator, the diagnostic clock must also be enabled. Set the

DIAG_CLK_EN bit (PHY_CTRL_1 register, Address 0x0012, Bit 2).

Table 85. Bit Descriptions for FG_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_EN

When set, this bit enables the built-in frame generator.

0x0

R/W

Frame Generator Control and Restart Register

Address: 0x9416, Reset: 0x0001, Name: FG_CNTRL_RSTRT

This register provides frame generator control and restart functions.

Table 86. Bit Descriptions for FG_CNTRL_RSTRT

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x0

FG_RSTRT

When set, this bit restarts the frame generator. This bit is self clearing.

0x0

R/W

[2:0]

FG_CNTRL

This bit field controls the frame generator in accordance with the following encoding:

0x1

R/W

111: reserved.

110: reserved.

101: data field decrementing from 255 (decimal) to 0.

100: alternative 0x55 in the MAC client data frame field.

011: all ones in the MAC client data frame field.

010: all zeros in the MAC client data frame field.

001: random number in the MAC client data frame field.

000: no frames after completion of current frame.

ADIN1300CCPZ-R7 Folha de dados(PDF) 63 Page - Analog Devices

ADIN1300CCPZ-R7 Folha de dados(HTML) 63 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Folha de dados Download

Ligação URL