ADIN1300CCPZ-R7 datasheet(73/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 73 of 79

Subsystem Software Reset Configuration Enable Register

Address: 0xFF0D, Reset: 0x0000, Name: GE_SFT_RST_CFG_EN

In the event of a software reset using the GE_SFT_RST bit, the subsystem behavior depends on the setting of this register bit.

Table 117. Bit Descriptions for GE_SFT_RST_CFG_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

GE_SFT_RST_CFG_EN

In the event of a subsystem software reset using the GE_SFT_RST bit, the subsystem

behavior depends on the setting of the GE_SFT_RST_CFG_EN bit.

0x0

R/W

1: when the GE_SFT_RST_CFG_EN bit is set, the subsystem requests a new set of

hardware configuration pin settings from the chip during the software reset sequence.

0: when GE_SFT_RST_CFG_EN is clear, the previously stored hardware configuration

pin settings are reloaded into the corresponding management registers.

Subsystem Clock Configuration Register

Address: 0xFF1F, Reset: 0x0000, Name: GE_CLK_CFG

This register allows the subsystem output clock configuration to be controlled.

Table 118. Bit Descriptions for GE_CLK_CFG

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

GE_CLK_RCVR_125_EN

When this bit is set, the125 MHz PHY recovered clock (or PLL clock) is driven at the

GP_CLK pin.

0x0

R/W

GE_CLK_FREE_125_EN

When this bit is set, the 125 MHz PHY free running clock is driven at the GP_CLK pin.

0x0

R/W

GE_REF_CLK_EN

When this bit is set, the 25 MHz reference clock from the crystal oscillator is driven at

the CLK25_REF pin. Note that when an external 50 MHz clock is driven at XTAL_I (for

RMII), it is divided by 2, and the divided 25 MHz reference clock is driven at the

CLK25_REF pin.

0x0

R/W

GE_CLK_HRT_RCVR_EN

The PHY provides a digital recovered heartbeat clock. This clock is sourced from

either the 25 MHz reference clock or the 125 MHz recovered clock depending on the

mode that the PHY is in and on the settings of certain registers. Setting

GE_CLK_HRT_RCVR_EN causes the subsystem to request the chip to drive the digital

recovered heartbeat clock at the GP_CLK pin.

0x0

R/W

GE_CLK_HRT_FREE_EN

The PHY provides a digital free running heartbeat clock. This clock is sourced either

from the 25 MHz reference clock or the 125 MHz free running clock depending on

the mode that the PHY is in and on the settings of certain registers. Setting

GE_CLK_HRT_FREE_EN causes the subsystem to request the chip to drive the digital

free running heartbeat clock at the GP_CLK pin.

0x0

R/W

GE_CLK_25_EN

When this bit is set, the 25 MHz reference clock from the crystal oscillator is driven at

the GP_CLK pin (having been processed through the digital block, and is not as clean

as the equivalent clock available at the CLK25_REF pin).

0x0

R/W

Subsystem RGMII Configuration Register

Address: 0xFF23, Reset: 0x0E07, Name: GE_RGMII_CFG

This register allows the MAC interface RGMII configuration to be controlled.

Table 119. Bit Descriptions for GE_RGMII_CFG

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x1

GE_RGMII_100_LOW_LTNCY_EN

Enable/Disable Low RGMII Latency for 100BASE-TX.

0x1

R/W

1: enable low RGMII latency for 100BASE-TX.

0: disable low RGMII latency for 100BASE-TX.

GE_RGMII_10_LOW_LTNCY_EN

Enable/Disable Low RGMII Latency for 10BASE-T.

0x1

R/W

1: enable low RGMII latency for 10BASE-T.

0: disable low RGMII latency for 10BASE-T.

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