ADIN1300CCPZ-R7 datasheet(61/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 61 of 79

Frame Checker Maximum Frame Size Register

Address: 0x9408, Reset: 0x05F2, Name: FC_MAX_FRM_SIZE

This register specifies the maximum frame size. Frames longer than this size are counted as oversized frames.

Table 73. Bit Descriptions for FC_MAX_FRM_SIZE

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_MAX_FRM_SIZE

This bit field specifies the max frame size. Received frames that are longer than this are

counted as oversized frames. Note, this frame length excludes the preamble and start

frame delimiter.

0x5F2

R/W

Frame Checker Count High Register

Address: 0x940A, Reset: 0x0000, Name: FC_FRM_CNT_H

This register is a latched copy of Bits[31:16] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT

register, Address 0x0014) is read, the receive frame counter register is latched. A copy of the receive frame counter register is latched when

recant is read so that the error count and receive frame count are synchronized.

Table 74. Bit Descriptions for FC_FRM_CNT_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FRM_CNT_H

Bits[31:16] of Latched Copy of the Number of Received Frames.

0x0

Frame Checker Count Low Register

Address: 0x940B, Reset: 0x0000, Name: FC_FRM_CNT_L

This register is a latched copy of Bits[15:0] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT

register, Address 0x0014) is read, the receive frame counter register is latched. A copy of the receive frame counter register is latched when

RX_ERR_CNT is read so that the error count and receive frame count are synchronized.

Table 75. Bit Descriptions for FC_FRM_CNT_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FRM_CNT_L

Bits[15:0] of Latched Copy of the Number of Received Frames.

0x0

Frame Checker Length Error Count Register

Address: 0x940C, Reset: 0x0000, Name: FC_LEN_ERR_CNT

This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error

status. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the frame length error counter register is

latched, which ensures that the frame length error count and receive frame count are synchronized.

Table 76. Bit Descriptions for FC_LEN_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_LEN_ERR_CNT

Latched Copy of the Frame Length Error Counter.

0x0

Frame Checker Alignment Error Count Register

Address: 0x940D, Reset: 0x0000, Name: FC_ALGN_ERR_CNT

This register is a latched copy of the frame alignment error counter register. This register is a count of received frames with an alignment

error status. When the receive error counter (RX_ERR_CNT register, Address 0x0014) is read, the alignment error counter register is

latched, which ensures that the frame alignment error count and receive frame count are synchronized.

Table 77. Bit Descriptions for FC_ALGN_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ALGN_ERR_CNT

Latched Copy of the Frame Alignment Error Counter.

0x0

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