ADIN1300CCPZ-R7 datasheet(53/79 Pages) AD

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Data Sheet

ADIN1300

Rev. 0 | Page 53 of 79

PHY Status 1 Register

Address: 0x001A, Reset: 0x0300, Name: PHY_STATUS_1

This register provides access to various PHY status registers.

Table 53. Bit Descriptions for PHY_STATUS_1

Bits

Bit Name

Description

Reset

Access

PHY_IN_STNDBY

A 1 indicates that the PHY is in standby state and does not attempt to bring up links. The

standby state can be used to run diagnostics, including cable diagnostics.

0x0

MSTR_SLV_FLT_STAT

Master Slave Configuration Fault Status Bit. A 1 indicates that a fault has occurred in the

resolution of master/slave. This bit is a copy of MSTR_SLV_FLT, (MSTR_SLAV_STATUS register,

Address 0x000A). Reading the MSTR_SL_FLT_STAT bit does not clear MSTR_SLV_FLT.

0x0

PAR_DET_FLT_STAT

Parallel Detection Fault Status Bit. A 1 indicates that a fault has occurred in the parallel

detection process. This bit is a copy of PAR_DET_FLT, (AUTONEG_EXP register,

Address 0x0006). Reading the PAR_DET_FLT_STAT bit does not clear PAR_DET_FLT.

0x0

AUTONEG_STAT

Autonegotiation Status Bit. A 1 indicates that autonegotiation has completed. This bit is

a copy of AUTONEG_DONE (MII_STATUS register, Address 0x0001). Reading the

AUTONEG_STAT bit does not clear AUTONEG_DONE.

0x0

PAIR_01_SWAP

A 1 indicates that Pair 0 and Pair 1 have been swapped.

0x0

B_10_POL_INV

A 1 indicates that the polarity of the 10BASE-T signal has been inverted.

0x0

[9:7]

HCD_TECH

This field indicates the resolved technology after the link is established.

0x6

111: reserved.

110: reserved.

101: speed resolved to 1000BASE-T full duplex.

100: speed resolved to 1000BASE-T half duplex.

011: speed resolved to 100BASE-TX full duplex.

010: speed resolved to 100BASE-TX half duplex.

001: speed resolved to 10BASE-T full duplex.

000: speed resolved to 10BASE-T half duplex.

LINK_STAT

A 1 indicates that a link is up.

0x0

TX_EN_STAT

A 1 indicates that transmit enable (TX_EN) is asserted.

0x0

RX_DV_STAT

A 1 indicates that receive data valid (RX_DV) is asserted.

0x0

COL_STAT

A 1 indicates that collision is asserted.

0x0

AUTONEG_SUP

A 1 indicates that both the local and remote PHYs support autonegotiation.

0x0

LP_PAUSE_ADV

A 1 indicates that the link partner has advertised pause. The link partner pause

advertisement bit indicates that the link partner advertised support for pause operation

on full duplex links. This bit provides the same information as LP_PAUSE_ABLE.

0x0

LP_APAUSE_ADV

A 1 indicates that the link partner has advertised asymmetric pause. The link partner

asymmetric pause advertisement bit indicates that the link partner advertised support

for asymmetric pause operation on full duplex links. This bit provides the same

information as LP_APAUSE_ABLE.

0x0

LED Control 1 Register

Address: 0x001B, Reset: 0x0001, Name: LED_CTRL_1

This register provides access to various PHY LED control register bits.

Table 54. Bit Descriptions for LED_CTRL_1

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

R/W

LED_A_EXT_CFG_EN

Enable Extended Configuration Set for LED_0 Pin. Also see LED_CTRL_2 register,

Address 0x001C, Bits[3:0].

0x0

R/W

1: enable extended configuration set for LED_0 pin.

0: disable extended configuration set for LED_0 pin.

[9:8]

RESERVED

Reserved.

0x0

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