ADIN1300CCPZ-R7 datasheet(42/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 42 of 79

Bits

Bit Name

Description

Reset

Access

COLTEST

Collision Test Bit.

0x0

R/W

1: enable collision signal test.

0: disable collision signal test.

SPEED_SEL_MSB

See SPEED_SEL_LSB Bit Description.

0x1

R/W

11: reserved.

10: 1 Gbps.

01: 100 Mbps.

00: 10 Mbps.

UNIDIR_EN

The unidirectional enable register bit is read only and always reads as 1'b0. Transmission from

the media independent interface is only enabled when the PHY has determined that a valid

link has been established.

0x0

[4:0]

RESERVED

Reserved.

0x0

MII Status Register

Address: 0x0001, Reset: 0x7949, Name: MII_STATUS

This address corresponds to the MII status register specified in Clause 22.2.4.2 of IEEE Standard 802.3.

Table 32. Bit Descriptions for MII_STATUS

Bits

Bit Name

Description

Reset

Access

T_4_SPRT

The 100BASE-T4 ability bit always reads as 1'b0 because the PHY does not support

100BASE-T4.

0x0

FD_100_SPRT

The 100BASE-TX full duplex ability bit always reads as 1'b1 because the PHY supports

100BASE-TX full duplex.

0x1

HD_100_SPRT

The 100BASE-TX half duplex ability bit always reads as 1'b1 because the PHY supports

100BASE-TX half duplex.

0x1

FD_10_SPRT

The 10BASE-T full duplex ability bit always reads as 1'b1 because the PHY supports

10BASE-T full duplex.

0x1

HD_10_SPRT

The 10BASE-T half duplex ability bit always reads as 1'b1 because the PHY supports

10BASE-T half duplex.

0x1

FD_T_2_SPRT

The 100BASE-T2 full duplex ability bit always reads as 1'b0 because the PHY does not

support 100BASE-T2.

0x0

HD_T_2_SPRT

The 100BASE-T2 half duplex ability bit always reads as 1'b0 because the PHY does not

support 100BASE-T2.

0x0

EXT_STAT_SPRT

The extended status support bit always reads as 1'b1, indicating that the PHY provides

extended status information in Register 0x000F.

0x1

UNIDIR_ABLE

When zero, the unidirectional ability register bit indicates that the PHY can only

transmit data from the media independent interface when it has determined that a

valid link has been established. This bit always reads as 1'b0.

0x0

MF_PREAM_SUP_ABLE

Management Frame Preamble Suppression Ability Bit. This always reads as 1'b1

because the PHY accepts management frames with preamble suppressed.

0x1

AUTONEG_DONE

Autonegotiation Complete Bit.

0x0

1: autonegotiation process completed.

0: autonegotiation process not completed.

REM_FLT_LAT

Remote Fault Bit. When this bit goes high, it latches high until it is unlatched by reading.

0x0

1: remote fault condition detected.

0: no remote fault condition detected.

AUTONEG_ABLE

Autonegotiation Ability Bit. This bit always reads as 1'b1.

0x1

1: PHY is able to perform autonegotiation.

0: PHY is not able to perform autonegotiation.

LINK_STAT_LAT

Link Status Bit. If the link subsequently drops, this bit latches low until it is unlatched by

reading.

0x0

1: link is up.

0: link is down.

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