ADIN1300CCPZ-R7 datasheet(29/79 Pages) AD

29 / 79 page

Data Sheet

ADIN1300

Rev. 0 | Page 29 of 79

Forced/Advertised PHY Speed

As outlined in Table 23, it is possible to advertise all or a subset

of PHY speed capabilities, select preferred slave or master, set

half duplex or full duplex mode, and enable or disable

autonegotiation.

Autonegotiation is enabled for the first 11 rows in Table 23, such

as in the case of advertised speeds modes. It is also possible to

configure forced speed modes where autonegotiation is disabled

and the speed is forced (Row 12 to Row 14 of Table 23).

Referring to Table 23, three of the PHY_CFG1 and PHY_CFG0

hardware configuration pin settings result in the same link

speed configuration (Row 1, Row 2, and Row 4). However, Row 1

also enables three other functions, Row 2 does not enable any

extra functions, and in Row 4, the ADIN1300 is configured to

enter software power-down mode after reset. The enabling or

disabling of autonegotiation and advertised speed settings can

also be set using the standard IEEE registers, MII_CONTROL

(Address 0x0000), AUTONEG_ADV (Address 0x0004), and

MSTR_SLV_CONTROL (Address 0x0009).

Software Power-Down after Reset

If the ADIN1300 is configured so that it does not enter software

power-down mode after reset, the ADIN1300 attempts to bring

up links at the configured speeds and MDI/MDIX configuration

after it exits reset. If the ADIN1300 is configured so that it enters

software power-down mode after reset (Row 4), the ADIN1300

waits in software power-down until it is configured over the

MDIO interface, at which point the PHY configuration can be

set to exit software power-down by software. The ADIN1300

can also be put into software power-down mode by setting the

SFT_PD bit (MII_CONTROL register, Address 0x0000).

Downspeed Configuration

If downspeed is enabled, the PHY down speeds to a lower speed

after a number of attempts if it cannot link at the highest speed

advertised. The use of downspeed requires autonegotiation to be

enabled with multiple speeds advertised. The default operation

of downspeed can be overwritten in software by writing to DN_

SPEED_TO_100_EN (PHY_CTRL_2 register, Address 0x0016,

Bit 11), DN_SPEED_TO_10_EN (PHY_CTRL_2 register,

Address 0x0016, Bit 10), and NUM_SPEED_RETRY

(PHY_CTRL_3 register, Address 0x0017, Bits[12:10]).

Energy Detect Power-Down Configuration

If energy detect power-down is enabled and no energy is

detected at the MDI pins, the ADIN1300 enters a low power

mode. Therefore, this mode saves power where there is no cable

connected or the remote PHY is powered down.

Energy Efficient Ethernet

If EEE is enabled and also advertised by the remote PHY, the

ADIN1300 can enter a low power mode (low power idle) when

no data is being transmitted by either end. See the EEE, Low

Power Idle Mode section for more details.

Auto MDIX Configuration

Auto MDIX configuration mode is shared with the GP_CLK pin

and can be configured according to Table 24. This pin does not

have an internal pull-up resistor, so external resistors must be

used to set the MDI/MDIX mode.

Table 24. Auto MDIX Configuration

Configuration

MDIX_MODE

Manual MDI

MODE_1

Manual MDIX

MODE_2

Auto MDIX, Prefer MDIX

MODE_3

Auto MDIX, Prefer MDI

MODE_4

If auto MDIX is enabled (MODE_3 or MODE_4), the ADIN1300

automatically determines if the MDI or MDIX configuration

must be used. Otherwise, the ADIN1300 is forced to the chosen

MDI or MDIX configuration.

If enabling auto MDIX, the ADIN1300 supports auto MDIX with

a preference for MDI or MDIX. This determines which MDI/

MDIX setting is first in the autocrossover algorithm. To achieve a

faster MDI/MDIX resolution in some cases, set both PHYs to

the same preferred configuration (MDI or MDIX) when a

crossover cable is used, and to opposite preferred configurations if

a straight-through cable is used, which has the advantage of still

being able to work with a mismatch of wiring and optimize the

time to resolve auto MDIX.

The default operation of auto MDIX can be overwritten in

software by writing to the AUTO_MDI_EN bit (PHY_CTRL_1

(PHY_CTRL_1 register, Address 0x0012).

MAC Interface Selection

The MAC interface selection is shared with the RX_CTL/RX_DV/

CRS_DV pin and RXC/RX_CLK pin, and can be configured

according to Table 25. In RGMII mode, it is possible to enable a

2 ns internal delay on RXC only or on both RXC and TXC. The

RX_CTL/RX_DV/CRS_DV pin and RXC/RX_CLK pin have

weak internal pull-down resistors. Therefore, by default, the

ADIN1300 is configured in RGMII mode with a 2 ns delay on

RXC and TXC. External resistors must be used to select any of

the remaining MAC interface modes.

The MAC interface selection can also be done via software (GE_

RGMII_CFG and GE_RMII_CFG registers) with the internal 2 ns

delay configured via the GE_RGMII_RXLD_EN bit and GE_

RGMII_TXLD_EN bit within the GE_RGMII_CFG register

(Address 0xFF23). Put the PHY in software power-down by

setting the SFT_PD bit (MII_CONTROL register, Address 0x0000)

before any changes are made to the MAC interface configuration

registers. Because RMII mode requires a 50 MHz reference clock,

do not use software to configure the MAC interface to RMII.

Table 25. MAC Interface Selection

MAC Interface Selection

MACIF_SEL1

MACIF_SEL0

RGMII RXC/TXC 2 ns Delay

Low

RGMII RXC Only, 2 ns Delay

High

Low

MII

Low

High

RMII

High

ADIN1300CCPZ-R7 Folha de dados(PDF) 29 Page - Analog Devices

ADIN1300CCPZ-R7 Folha de dados(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Folha de dados Download

Ligação URL