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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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ADIN1300CCPZ-R7 Folha de dados(PDF) 8 Page - Analog Devices |
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ADIN1300CCPZ-R7 Folha de dados(HTML) 8 Page - Analog Devices |
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8 / 79 page  ADIN1300 Data Sheet Rev. 0 | Page 8 of 79 TX_CLK TXD_0 TO TXD_3 TX_EN TX_ER t2 t3 t1 t5 t6 t4 t4 Figure 5. MII Transmit Timing Table 6. MII 100BASE-TX Receive Timing Parameter Description Min Typ Max Unit t1 RX_CLK period 40 ns t2 RX_CLK high time 16 20 24 ns t3 RX_CLK low time 16 20 24 ns t4 RX_CLK rise/fall time 1 ns t5 MII output signal (RXD_0 to RXD_3, RX_EN, RX_ER) setup time to RX_CLK 10 ns t6 MII output signal (RXD_0 to RXD_3, RX_EN, RX_ER) hold time to RX_CLK 10 ns RX_CLK RXD_0 TO RXD_3 RX_EN RX_ER t2 t3 t1 t5 t6 t4 t4 Figure 6. MII Receive Timing Table 7. MII 10BASE-Te Transmit Timing (see Figure 5) Parameter Description Min Typ Max Unit t1 TX_CLK period 400 ns t2 TX_CLK high time 140 200 260 ns t3 TX_CLK low time 140 200 260 ns t4 TX_CLK rise/fall time 1 ns t5 MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) setup time to TX_CLK 10 ns t6 MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) hold time to TX_CLK 0 ns Table 8. MII 10BASE-Te Receive Timing (see Figure 6) Parameter Description Min Typ Max Unit t1 RX_CLK period 400 ns t2 RX_CLK high time 140 200 260 ns t3 RX_CLK low time 140 200 260 ns t4 RX_CLK rise/fall time 1 1 ns t5 MII output signal (RXD_0 to RXD_3, RX_EN, RX_ER) setup time to RX_CLK 10 ns t6 MII output signal (RXD_0 to RXD_3, RX_EN, RX_ER) hold time to RX_CLK 10 ns RGMII Transmit/Receive Table 9. RGMII Timing Parameter Description Min Typ Max Unit t1 Data to clock output skew (at transmitter)1 −500 0 +500 ps t2 Data to clock input skew (at receiver)1 1 1.8 2.6 ns t3 Data to clock output setup time (at transmitter – internal delay)2 1.2 2.0 ns t4 Clock to data output hold time (at transmitter – internal delay)2 1.2 2.0 ns t5 Data to clock input setup time (at receiver – internal delay)2 1.0 2.0 ns t6 Clock to data input hold time (at receiver – internal delay)2 1.0 2.0 ns tCYC Clock cycle duration3 7.2 8 8.8 ns |
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