ADIN1300CCPZ-R7 datasheet(72/79 Pages) AD

72 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 72 of 79

LED Pulse Stretching Duration Register

Address: 0xBC00, Reset: 0x0011, Name: LED_PUL_STR_DUR

When the LED_PUL_STR_DUR_SEL bit field in the LED_CTRL_1 register (Address 0x001B, Bits[3:2]) is set to 2'b11, the

LED_PUL_STR_DUR register determines the LED pulse stretching duration.

Table 114. Bit Descriptions for LED_PUL_STR_DUR

Bits

Bit Name

Description

Reset

Access

[15:6]

RESERVED

Reserved.

0x0

[5:0]

LED_PUL_STR_DUR

When the LED_PUL_STR_DUR_SEL bit field in the LED_CTRL_1 register (Address 0x001B,

Bits[3:2]) is set to 2'b11, the LED_PUL_STR_DUR bit field determines the LED pulse stretching

duration. Multiply the value specified by 8 to determine the duration in milliseconds.

0x11

R/W

SUBSYSTEM REGISTER SUMMARY

The subsystem registers are accessible at Device Address 0x1E using Clause 45 access. For systems that do not support the interface

specified under Clause 45, these registers can be accessed using Clause 22 access via Register 0x0010 and Register 0x0011.

The default value of some of the registers are determined by the value of the hardware configuration pins, which are read just after the

RESET_N pin is deasserted (see the Hardware Configuration Pins section) so that the default operation of the ADIN1300 can be

configured in unmanaged applications. The default values in the registers listed in Table 115 assume that the ADIN1300 is configured

with autonegotiation enabled, all speeds advertised, and the ADIN1300 is not configured to enter software power-down after reset.

Table 115. Subsystem Register Summary

Address

Name

Description

Reset

Access

0xFF0C

GE_SFT_RST

Subsystem Software Reset Register.

0x0000

R/W

0xFF0D

GE_SFT_RST_CFG_EN

Subsystem Software Reset Configuration Enable Register.

0x0000

R/W

0xFF1F

GE_CLK_CFG

Subsystem Clock Configuration Register.

0x0000

R/W

0xFF23

GE_RGMII_CFG

Subsystem RGMII Configuration Register.

0x0E07

R/W

0xFF24

GE_RMII_CFG

Subsystem RMII Configuration Register.

0x0116

R/W

0xFF26

GE_PHY_BASE_CFG

Subsystem PHY Base Configuration Register.

0x0C86

R/W

0xFF3C

GE_LNK_STAT_INV_EN

Subsystem Link Status Invert Enable Register.

0x0000

R/W

0xFF3D

GE_IO_GP_CLK_OR_CNTRL

Subsystem GP_CLK Pin Override Control Register.

0x0000

R/W

0xFF3E

GE_IO_GP_OUT_OR_CNTRL

Subsystem LINK_ST Pin Override Control Register.

0x0000

R/W

0xFF3F

GE_IO_INT_N_OR_CNTRL

Subsystem INT_N Pin Override Control Register.

0x0000

R/W

0xFF41

GE_IO_LED_A_OR_CNTRL

Subsystem LED_0 Pin Override Control Register.

0x0000

R/W

SUBSYSTEM REGISTER DETAILS

Subsystem Software Reset Register

Address: 0xFF0C, Reset: 0x0000, Name: GE_SFT_RST

The soft reset register is used to reset the subsystem.

Table 116. Bit Descriptions for GE_SFT_RST

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

GE_SFT_RST

The subsystem can be reset by setting GE_SFT_RST to 1. The subsystem behavior depends on

the setting of the GE_SFT_RST_CFG_EN register.

0x0

R/W

When the GE_SFT_RST_CFG_EN bit is set, the subsystem requests a new set of hardware

configuration pin settings from the chip during the software reset sequence. When

GE_SFT_RST_CFG_EN is clear, the previously stored hardware configuration pin settings are

reloaded into the corresponding management registers.

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