ADIN1300CCPZ-R7 datasheet(64/79 Pages) AD

64 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 64 of 79

Frame Generator Continuous Mode Enable Register

Address: 0x9417, Reset: 0x0000, Name: FG_CONT_MODE_EN

This register is used to put the frame generator into continuous mode. The default mode of operation is burst mode, where the number of

frames generated is specified by the FG_NFRM_H register and FG_NFRM_L register (Address 0x941C and Address 0x941D).

Table 87. Bit Descriptions for FG_CONT_MODE_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_CONT_MODE_EN

This bit is used to put the frame generator into continuous mode or burst mode.

0x0

R/W

1: frame generator operates in continuous mode. In this mode, the frame generator

keeps generating frames indefinitely.

0: frame generator operates in burst mode. In this mode, the frame generator generates

a single burst of frames and then stops. The number of frames in the burst is

determined by the FG_NFRM_H register and FG_NFRM_L register.

Frame Generator Interrupt Enable Register

Address: 0x9418, Reset: 0x0000, Name: FG_IRQ_EN

This register is used to enable the frame generator interrupt. An interrupt is generated when the requested number of frames has been

generated. Enable the frame checker/generator interrupt in the IRQ_MASK register. Set the FC_FG_IRQ_EN bit (Address 0x0018, Bit 7).

The interrupt status can be read via the IRQ_STATUS register, FC_FG_IRQ_STAT bit (Address 0x0019, Bit 7).

Table 88. Bit Descriptions for FG_IRQ_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

FG_IRQ_EN

When set, this bit indicates that the frame generator must generate an interrupt when it has

transmitted the programmed number of frames.

0x0

R/W

1: enable the frame generator interrupt.

0: disable the frame generator interrupt.

Frame Generator Frame Length Register

Address: 0x941A, Reset: 0x006B, Name: FG_FRM_LEN

This register specifies the MAC client data field frame length in bytes. In addition to the data field, 6 bytes are added for the source

address, 6 bytes for the destination address, 2 bytes for the length field, and 4 bytes for the frame check sequence (FCS). The total frame

length is the data field length plus 18.

Table 89. Bit Descriptions for FG_FRM_LEN

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_FRM_LEN

The Data Field Frame Length in Bytes.

0x6B

R/W

Frame Generator Number of Frames High Register

Address: 0x941C, Reset: 0x0000, Name: FG_NFRM_H

This register is Bits[31:16] of a 32-bit register that specifics the number of frames to be generated each time the frame generator is enabled

or restarted.

Table 90. Bit Descriptions for FG_NFRM_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FG_NFRM_H

Bits[31:16] of the Number of Frames to be Generated.

0x0

R/W

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