ADIN1300CCPZ-R7 datasheet(28/79 Pages) AD

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ADIN1300

Data Sheet

Rev. 0 | Page 28 of 79

PHY Configuration

The PHY_CFG1 and PHY_CFG0 hardware configuration pins

are shared with the LINK_ST and LED_0 functional pins,

respectively. These hardware configuration pins cover the

following functions and can be configured according to Table 23:

•

Forced/advertised PHY speed

•

Software power-down mode after reset

•

Downspeed enable

•

Energy detect power-down (EDPD) mode

•

EEE enable

The PHY_CFG1 pin and PHY_CFG0 pin have no internal pull-

up resistors, so external resistors must be used to configure

these functions.

Table 23. PHY Configuration

Forced/

Advertised

PHY Speed Configuration

Other Functions

Enabled1

PHY_CFG1

PHY_CFG0

Row

No.

Advertised Speeds

(Autonegotiation Enabled)

10 half duplex (HD)/full duplex (FD),

100 HD/FD, and 1000 FD slave

Downspeed,

EDPD, and EEE

MODE_4

10 HD/FD, 100 HD/FD, and 1000 FD slave

MODE_1

MODE_4

10 HD/FD, 100 HD/FD, and 1000 FD master

MODE_2

MODE_4

10 HD/FD, 100 HD/FD, and 1000 FD slave

Software power-down

mode after reset

MODE_3

MODE_4

10 HD/FD and 100 HD/FD

MODE_4

MODE_2

10 FD and 100 FD

MODE_4

MODE_3

100 FD and 1000 FD slave

MODE_4

MODE_1

100 FD and 1000 FD master

MODE_3

MODE_1

100 FD

MODE_1

1000 FD slave

MODE_2

MODE_1

1000 FD master

MODE_3

MODE_2

Forced Speed

(Autonegotiation Disabled)

10 FD

MODE_1

MODE_2

100 HD

MODE_2

100 FD

MODE_3

If no function is listed in this column, then only the PHY speed is configured using this row.

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