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RA4L1 Folha de dados(PDF) 119 Page - Renesas Technology Corp |
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RA4L1 Folha de dados(HTML) 119 Page - Renesas Technology Corp |
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119 / 125 page ![]() Appendix 3. I/O Registers This appendix describes I/O register address and access cycles by function. 3.1 Peripheral Base Addresses This section provides the base addresses for peripherals described in this manual. Table A3.1 shows the name, description, and the base address of each peripheral. Table A3.1 Peripheral base address (1 of 2) Name Description Base address RMPU Master Memory Protection Unit 0x4000_0000 TZF TrustZone Filter 0x4000_0E00 SRAM Special Function Register 0x4000_2000 BUS BUS Control 0x4000_3000 DMAC0 Direct memory access controller 0 0x4000_5000 DMAC1 Direct memory access controller 1 0x4000_5040 DMAC2 Direct memory access controller 2 0x4000_5080 DMAC3 Direct memory access controller 3 0x4000_50C0 DMAC4 Direct memory access controller 4 0x4000_5100 DMAC5 Direct memory access controller 5 0x4000_5140 DMAC6 Direct memory access controller 6 0x4000_5180 DMAC7 Direct memory access controller 7 0x4000_51C0 DMA DMAC Module Activation 0x4000_5200 DTC Data Transfer Controller 0x4000_5400 ICU Interrupt Controller 0x4000_6000 CACHE CACHE 0x4000_7000 CPSCU CPU System Security Control Unit 0x4000_8000 DBG Debug Function 0x4001_B000 FCACHE Flash Security Attribution Control 0x4001_C100 SYSC System Control 0x4001_E000 PORT0 Port 0 Control Registers 0x4001_F000 PORT1 Port 1 Control Registers 0x4001_F020 PORT2 Port 2 Control Registers 0x4001_F040 PORT3 Port 3 Control Registers 0x4001_F060 PORT4 Port 4 Control Registers 0x4001_F080 PORT5 Port 5 Control Registers 0x4001_F0A0 PORT6 Port 6 Control Registers 0x4001_F0C0 PORT7 Port 7 Control Registers 0x4001_F0E0 PORT8 Port 8 Control Registers 0x4001_F100 PFS Pmn Pin Function Control Register 0x4001_F800 ELC Event Link Controller 0x4008_2000 RTC Realtime Clock 0x4008_3000 IWDT Independent Watchdog Timer 0x4008_3200 WDT Watchdog Timer 0x4008_3400 CAC Clock Frequency Accuracy Measurement Circuit 0x4008_3600 RA4L1 Datasheet Appendix 3. I/O Registers R01DS0447EJ0131 Rev.1.31 May 26, 2026 Page 119 of 125 |
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