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HD6433636SW Folha de dados(PDF) 202 Page - Renesas Technology Corp |
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HD6433636SW Folha de dados(HTML) 202 Page - Renesas Technology Corp |
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202 / 418 page ![]() 188 Bit 4—Input Capture Interrupt Edge Select (IIEGS): Bit 4 selects the input signal edge at which input capture interrupts are requested. Bit 4: IIEGS Description 0 Interrupts are requested at the rising edge of the input capture signal (initial value) 1 Interrupts are requested at the falling edge of the input capture signal Bits 3, 2—Counter Clear 1, 0 (CCLR1, CCLR0): Bits 3 and 2 designate whether TCG is cleared at the rising, falling, or both edges of the input capture signal, or is not cleared. Bit 3: CCLR1 Bit 2: CCLR0 Description 0 0 TCG is not cleared (initial value) 1 TCG is cleared at the falling edge of the input capture signal 1 0 TCG is cleared at the rising edge of the input capture signal 1 TCG is cleared at both edges of the input capture signal Bits 1, 0—Clock Select (CKS1, CKS0): Bits 1 and 0 select the clock input to TCG from four internal clock signals. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 Internal clock: ø/64 (initial value) 1 Internal clock: ø/32 1 0 Internal clock: ø/2 1 Internal clock: ø W/2 |
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