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HD6433636SW Folha de dados(PDF) 84 Page - Renesas Technology Corp |
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HD6433636SW Folha de dados(HTML) 84 Page - Renesas Technology Corp |
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84 / 418 page ![]() 70 3.3.4 Internal Interrupts There are 17 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted, the I bit in CCR is set to 1. Vector numbers 10 to 20 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt controller Interrupt request CCR (CPU) I External or internal interrupts External interrupts or internal interrupt enable signals Figure 3.2 Block Diagram of Interrupt Controller |
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