HD6433636SW datasheet(204/418 Pages) RENESAS

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Figure 9.8 shows a typical timing diagram for the noise canceller circuit. In this example, a high-

level input at the input capture pin is rejected as noise because its pulse width is less than five

sampling clock ø cycles.

Input capture

input signal

Sampling

clock

Noise canceller

output

Rejected as noise

Figure 9.8 Noise Canceller Circuit Timing (Example)

9.4.4

Timer Operation

Timer G Functions: Timer G is an 8-bit up-counter that functions as an input capture timer or an

interval timer. These two functions are described below.

• Input capture timer operation

Timer G functions as an input capture timer when bit TMIG of port mode register 1 (PMR1) is

set to 1.*

At reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF

(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.

Immediately after reset, TCG begins counting an internal clock with a frequency of ø divided

by 64 (ø/64). The clock to be input can be selected by using bits CKS1 and CKS0 in TMG

from four internal clock sources.

At the rising edge/falling edge of the input capture signal input to pin TMIG, the value of TCG

is copied into ICRGR/ICRGF. If the input edge is the same as the edge selected by the IIEGS

bit of TMG, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, a CPU

interrupt is requested. For details on interrupts, see 3.3, Interrupts.

TCG can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture

signal as determined with bits CCLR1 and CCLR0 of TMG. If TCG overflows while the input

capture signal is high, bit OVFH of TMG is set. If TCG overflows while the input capture

signal is low, bit OVFL of TMG is set. When either of these bits is set, if bit OVIE of TMG is

currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2,

then timer G requests a CPU interrupt. For further details see 3.3, Interrupts.

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