HD6433636SW datasheet(81/418 Pages) RENESAS

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Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)

Bit 7: IRRDT

Description

[Clearing conditions]

(initial value)

When IRRDT = 1, it is cleared by writing 0

[Setting conditions]

When DTON = 1 and a direct transfer is made immediately after a SLEEP

instruction is executed

Bit 6—A/D Converter Interrupt Request Flag (IRRAD)

Bit 6: IRRAD

Description

[Clearing conditions]

(initial value)

When IRRAD = 1, it is cleared by writing 0

[Setting conditions]

When A/D conversion is completed and ADSF is reset

Bit 5—Reserved Bit: Bit 5 is reserved: it is always read as 0, and should be used cleared to 0.

Bit 4—Timer G Interrupt Request Flag (IRRTG)

Bit 4: IRRTG

Description

[Clearing conditions]

(initial value)

When IRRTG = 1, it is cleared by writing 0

[Setting conditions]

When pin TMIG is set to TMIG input and the designated signal edge is

detected, or when TCG overflows (from H’FF to H’00) while TMG OVIE is set

to 1

Bit 3—Timer FH Interrupt Request Flag (IRRTFH)

Bit 3: IRRTFH

Description

[Clearing conditions]

(initial value)

When IRRTFH = 1, it is cleared by writing 0

[Setting conditions]

When counter FH matches output compare register FH in 8-bit timer mode, or

when 16-bit counter F (TCFL, TCFH) matches output compare register F

(OCRFL, OCRFH) in 16-bit timer mode

HD6433636SW Folha de dados(PDF) 81 Page - Renesas Technology Corp