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HD6433636SW Folha de dados(PDF) 206 Page - Renesas Technology Corp |
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HD6433636SW Folha de dados(HTML) 206 Page - Renesas Technology Corp |
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206 / 418 page ![]() 192 • Timing with noise canceller function enabled When input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. Figure 9.10 shows the timing. External input capture signal Sampling clock Noise canceller circuit output Internal input capture signal R Figure 9.10 Input Capture Signal Timing (Noise Canceller Function Enabled) Timing of Input Capture: Figure 9.11 shows the input capture timing in relation to the internal input capture signal. Internal input capture signal TCG Input capture register N –1 N N +1 H'XX N Figure 9.11 Input Capture Timing |
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