HD6433636SW datasheet(201/418 Pages) RENESAS

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187

Timer Mode Register G (TMG)

Bit

76543210

OVFH

OVFL

OVIE

IIEGS

CCLR1

CCLR0

CKS1

CKS0

Initial value

00000000

Read/Write

R/W*

R/W

Note: * Only 0 can be written, to clear flag.

TMG is an 8-bit read/write register. It controls the choice of four internal clocks, counter clear

selection, and edge selection for input capture interrupt requests. It also indicates overflow status

and enables or disables overflow interrupt requests.

Upon reset, TMG is initialized to H'00.

Bit 7—Timer Overflow Flag H (OVFH): Bit 7 is a status flag indicating that TCG overflowed

(from H'FF to H'00) when the input capture signal was high. This flag is set by hardware and

cleared by software. It cannot be set by software.

Bit 7: OVFH

Description

[Clearing conditions]

(initial value)

After reading OVFH = 1, cleared by writing 0 to OVFH

[Setting conditions]

Set when the value of TCG overflows from H'FF to H'00

Bit 6—Timer Overflow Flag L (OVFL): Bit 6 is a status flag indicating that TCG overflowed

(from H'FF to H'00) when the input capture signal was low, or in interval timer operation. This

flag is set by hardware and cleared by software. It cannot be set by software.

Bit 6: OVFL

Description

[Clearing conditions]

(initial value)

After reading OVFL = 1, cleared by writing 0 to OVFL

[Setting conditions]

Set when the value of TCG overflows from H'FF to H'00

Bit 5—Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables TCG overflow

interrupts.

Bit 5: OVIE

Description

TCG overflow interrupt disabled

(initial value)

TCG overflow interrupt enabled

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