HD6433636SW datasheet(79/418 Pages) RENESAS

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Bit 2—Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare

match and overflow interrupt requests.

Bit 2: IENTFL

Description

Disables timer FL interrupts

(initial value)

Enables timer FL interrupts

Bit 1—Timer Y Interrupt Enable (IENTY): Bit 1 enables or disables timer Y overflow

interrupt requests.

Bit 1: IENTY

Description

Disables timer Y interrupts

(initial value)

Enables timer Y interrupts

Bit 0—Reserved Bit: Bit 0 is reserved: it is always read as 1, and cannot be modified.

For details of SCI3 interrupt control, see Serial Control Register 3 (SCR3), in section 10.3.2.

Interrupt Request Register 1 (IRR1)

Bit

76543210

IRRTA

IRRS1

—

IRRI4

IRRI3

IRRI2

IRRI1

IRRI0

Initial value

00100000

Read/Write

R/W*

—

R/W*

Note: * Only a write of 0 for flag clearing is possible.

IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A,

SCI1, or IRQ

4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an

interrupt is accepted. It is necessary to write 0 to clear each flag.

Bit 7—Timer A Interrupt Request Flag (IRRTA)

Bit 7: IRRTA

Description

[Clearing conditions]

(initial value)

When IRRTA = 1, it is cleared by writing 0

[Setting conditions]

When the timer A counter value overflows (goes from H'FF to H'00)

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