HD6433636SW datasheet(200/418 Pages) RENESAS

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186

Input Capture Register GF (ICRGF)

Bit

76543210

ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0

Initial value

00000000

Read/Write

RRRRRRRR

ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is detected,

the TCG value at that time is transferred to ICRGF. If the input capture interrupt select bit (IIEGS)

is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit

IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on

interrupts are given in 3.3, Interrupts.

To ensure proper input capture when the noise canceller is not used, the pulse width of the input

capture signal should be at least 2ø or 2ø

SUB.

Upon reset, ICRGF is initialized to H'00.

Input Capture Register GR (ICRGR)

Bit

76543210

ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0

Initial value

00000000

Read/Write

RRRRRRRR

ICRGR is an 8-bit read-only register. When the rising edge of the input capture signal is detected,

the TCG value at that time is sent to ICRGR. If the IIEGS bit is cleared to 0 in TMG, bit IRRTG

in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable

Interrupts.

To ensure proper input capture when the noise canceller is not used, the pulse width of the input

capture signal should be at least 2ø or 2ø

SUB.

Upon reset, ICRGR is initialized to H'00.

HD6433636SW Folha de dados(PDF) 200 Page - Renesas Technology Corp