HD6433636SW datasheet(205/418 Pages) RENESAS

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Timer G has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin

TMIG. See 9.4.3, Noise Canceller Circuit, for details.

Note: * Rewriting the TMIG bit may cause an internal input capture signal to be generated.

• Interval timer operation

Timer G functions as an interval timer when bit TMIG is cleared to 0 in PMR1. Following a

reset, TCG starts counting cycles of the ø/64 internal clock. This is one of four internal clock

sources that can be selected by bits CKS1 and CKS0 of TMG. TCG counts up according to the

selected clock source. When it overflows from H'FF to H'00, bit OVFL of TMG is set to 1. If

bit OVIE of TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also

set to 1 in IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts.

Count Timing: TCG is incremented by input pulses from an internal clock. TMG bits CKS1 and

CKS0 select one of four internal clocks (ø/64, ø/32, ø/2, ø

W/2) derived by dividing the system

clock (ø) and the watch clock (ø

W).

Timing of Internal Input Capture Signals:

• Timing with noise canceller function disabled

Separate internal input capture signals are generated from the rising and falling edges of the

external input signal.

Figure 9.9 shows the timing of these signals.

External input

capture signal

Internal input

capture signal F

Internal input

capture signal R

Figure 9.9 Input Capture Signal Timing (Noise Canceller Function Disabled)

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