HD6433636SW datasheet(80/418 Pages) RENESAS

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Bit 6—SCI1 Interrupt Request Flag (IRRS1)

Bit 6: IRRS1

Description

[Clearing conditions]

(initial value)

When IRRS1 = 1, it is cleared by writing 0

[Setting conditions]

When an SCI1 transfer is completed

Bit 5—Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified.

Bits 4 to 0—IRQ

4 to IRQ0 Interrupt Request Flags (IRRI4 to IRRI0)

Bits 4 to 0:

IRRI4 to IRRI0

Description

[Clearing conditions]

(initial value)

When IRRIn = 1, it is cleared by writing 0 to IRRIn.

[Setting conditions]

IRRIn is set when pin

IRQ

n is set to interrupt input, and the designated signal

edge is detected.

(n = 4 to 0)

Interrupt Request Register 2 (IRR2)

Bit

76543210

IRRDT

IRRAD

—

IRRTG

IRRTFH

IRRTFL

IRRTY

IRRTYC

Initial value

00000001

Read/Write

R/W*

—

R/W*

RW*

Note: * Only a write of 0 for flag clearing is possible.

IRR2 is an 8-bit register containing direct transfer, A/D converter, timer G, timer FH, timer FL,

and timer Y interrupt flags. When a direct transfer, A/D converter, timer G, timer FH, timer FL, or

timer Y interrupt is requested, the corresponding flag is set to 1. The flags are not cleared

automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. However,

the timer Y interrupt request flag (IRRTY) is cleared by writing 0 to bit 0 (IRRTYC).

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