ADP1053ACPZ-R7 datasheet(11/84 Pages) AD

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Data Sheet

ADP1053

Rev. A | Page 11 of 84

Pin No.

Mnemonic

Description

SDA

PMBus/I2C Serial Data Input and Output (Open-Drain). This signal is referenced to AGND.

SCL

PMBus/I2C Serial Clock Input and Output (Open-Drain). This signal is referenced to AGND.

PSON_B

Power Supply On Input for Channel B. This signal is referenced to DGND.

CS ADC Input and Fast Current Sense Input for Overcurrent Protection and Current Monitoring. This signal is

referenced to AGND.

CS1_B

CS1 ADC Input and Fast Current Sense Input for Channel B. This signal is referenced to AGND.

PGOOD_B

Power-Good Output (Open-Drain) for Channel B. This signal is referenced to AGND. This pin is controlled by the

PGOOD_B flag and is driven low when the flag is set. The PGOOD_B flag is set when the POWER_SUPPLY_B, UVP_B,

EEPROM_CRC, or SOFTSTART_FILTER_B flag is set. The ACSNS and OTW2 flags can also be programmed to be included.

CS2+_B

Noninverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should

be 1 V for optimal operation.

CS2−_B

Inverting Input of the Differential Current Sense ADC for Channel B. The nominal voltage at this pin should be 1 V

for optimal operation.

OVP_B

Overvoltage Protection Comparator Input for Channel B. This signal is referenced to PGND_B.

PGND_B

Reference Pin for Channel B Overvoltage Protection (OVP_B).

VS−_B

Inverting Input of the Voltage Sense ADC for Channel B Loop Control. There should be a low ohmic connection

to AGND.

VS+_B

Noninverting Input of the Voltage Sense ADC for Channel B Loop Control. This signal is referenced to VS−_B.

FLGI/SYNI

Flag Input/Synchronization Input. When this pin is programmed as a flag input, an external signal can be input

to generate a flag condition. The polarity is configurable. When this pin is programmed as a synchronization

input, the input signal is used as a reference for the internal PWM frequencies. This signal is referenced to AGND.

FLGO/SYNO

Flag Output/Synchronization Output. When this pin is programmed as a flag output, it can be used to indicate

the light load mode operation. The polarity is configurable. When this pin is programmed as a synchronization

output, it can be used as a frequency reference for synchronization. This signal is referenced to AGND.

RTD2

Thermistor ADC Input from Zone 2. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed

from this pin to AGND. This signal is referenced to AGND.

DGND

IC Digital Ground. Reference ground for the digital circuitry of the ADP1053. This pin should be star-connected to

AGND.

VCORE

Output of 2.5 V Regulator. Connect a 330 nF capacitor between this pin and DGND.

VDD

Positive Supply Voltage, 3.0 V to 3.6 V. This signal is referenced to AGND. Connect a 330 nF capacitor from VDD to

AGND.

AGND

IC Common Analog Ground. This pin should be star-connected to DGND.

RES

Resistor Input. This pin sets the internal voltage reference for the ADP1053. Connect a 10 kΩ resistor (±1%) from

RES to AGND. This signal is referenced to AGND.

ADD

PMBus/I2C Address Select Input. Connect a resistor from ADD to AGND (see the PMBus/I2C Address section). This

signal is referenced to AGND.

RTD1

Thermistor ADC Input from Zone 1. Typically, a 100 kΩ thermistor in parallel with a 16.5 kΩ resistor are placed

from this pin to AGND. This signal is referenced to AGND.

Exposed Pad

The exposed pad on the underside of the package should be soldered to AGND.

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