ADP1053ACPZ-R7 datasheet(62/84 Pages) AD

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ADP1053

Data Sheet

Rev. A | Page 62 of 84

Table 77. Register 0xFE37—Channel B Light Load Mode Zero Setting

Bits

Bit Name

R/W

Description

[7:0]

Channel B light load

mode zero setting

R/W

This register specifies the position of the zero in the feedback filter for Channel B in light load

mode (see Figure 41).

Table 78. Register 0xFE38—Channel A Light Load Mode Pole Setting

Bits

Bit Name

R/W

Description

[7:0]

Channel A light load

mode pole setting

R/W

This register specifies the position of the pole in the feedback filter for Channel A in light load

mode (see Figure 41).

Table 79. Register 0xFE39—Channel B Light Load Mode Pole Setting

Bits

Bit Name

R/W

Description

[7:0]

Channel B light load

mode pole setting

R/W

This register specifies the position of the pole in the feedback filter for Channel B in light load

mode (see Figure 41).

Table 80. Register 0xFE3A—Channel A Light Load Mode High Frequency Gain

Bits

Bit Name

R/W

Description

[7:0]

Channel A light

load mode high

frequency gain

R/W

This register specifies the high frequency gain of the feedback filter for Channel A in light load

mode. The gain is programmable over a 20 dB range (see Figure 41). Each LSB corresponds to

a 0.3 dB increase.

Table 81. Register 0xFE3B—Channel B Light Load Mode High Frequency Gain

Bits

Bit Name

R/W

Description

[7:0]

Channel B light

load mode high

frequency gain

R/W

This register specifies the high frequency gain of the feedback filter for Channel B in light load

mode. The gain is programmable over a 20 dB range (see Figure 41). Each LSB corresponds to

a 0.3 dB increase.

Figure 42 illustrates the modulation limit settings. Register 0xFE3C and Register 0xFE3D configure the modulation limit for Channel A

and Channel B.

tRX

tFX

tRY

tFY

t0, START OF

SWITCHING CYCLE

tS/2

tS, END OF

SWITCHING CYCLE

tS/2

OUTX

OUTY

tMOD_LIMIT

Figure 42. Setting Modulation Limits

Table 82. Register 0xFE3C—Channel A Modulation Limit

Bits

Bit Name

R/W

Description

This register sets the maximum duty cycle modulation limit for PWM outputs in Channel A.

The modulation limit is the maximum time variation for the modulated edges from the default

timing (see Figure 42). The step size of an LSB depends on the switching frequency.

Switching Frequency

LSB Step Size

48.8 kHz to 86.8 kHz

80 ns

97.7 kHz to 183.8 kHz

40 ns

195.3 kHz to 378.8 kHz

[7:0]

Channel A

modulation limit

R/W

390.6 kHz to 625.0 kHz

20 ns

10 ns

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