ADP1053ACPZ-R7 datasheet(56/84 Pages) AD

56 / 84 page

ADP1053

Data Sheet

Rev. A | Page 56 of 84

CHANNEL A/CHANNEL B CURRENT SENSE AND LIMIT SETTING REGISTERS

Table 40. Register 0xFE10—CS1_A Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS1_A gain trim

R/W

This value calibrates the CS1_A current sense gain. For more information, see the CS, CS1_A, and

CS1_B Gain Trim section.

Table 41. Register 0xFE11—CS1_B Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS1_B gain trim

R/W

This value calibrates the CS1_B current sense gain. For more information, see the CS, CS1_A, and

CS1_B Gain Trim section.

Table 42. Register 0xFE12—CS2_A Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS2_A gain trim

R/W

This value calibrates the CS2_A current sense gain. For more information, see the CS2_A and

CS2_B Gain Trim section.

Table 43. Register 0xFE13—CS2_B Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS2_B gain trim

R/W

This value calibrates the CS2_B current sense gain. For more information, see the CS2_A and

CS2_B Gain Trim section.

Table 44. Register 0xFE14—CS2_A Digital Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

CS2_A digital offset

trim

R/W

This register contains the CS2_A digital offset trim level. This value is used to calibrate the CS2_A

value. For more information, see the CS2_A and CS2_B Offset Trim section.

Table 45. Register 0xFE15—CS2_B Digital Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

CS2_B digital offset

trim

R/W

This register contains the CS2_B digital offset trim level. This value is used to calibrate the CS2_B

value. For more information, see the CS2_A and CS2_B Offset Trim section.

Table 46. Register 0xFE16—CS2_A Analog Offset Trim

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

Analog trim polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[5:0]

CS2_A analog offset

trim

R/W

This value calibrates the CS2_A value. For more information, see the CS2_A and CS2_B Offset

Trim section.

Table 47. Register 0xFE17—CS2_B Analog Offset Trim

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

Analog trim polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[5:0]

CS2_B analog offset

trim

R/W

This value calibrates the CS2_B value. For more information, see the CS2_A and CS2_B Offset

Trim section.

ADP1053ACPZ-R7 Folha de dados(PDF) 56 Page - Analog Devices

ADP1053ACPZ-R7 Folha de dados(HTML) 56 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Folha de dados Download

Ligação URL