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ADP1053ACPZ-R7 Folha de dados(PDF) 77 Page - Analog Devices

Nome de Peças ADP1053ACPZ-R7
Descrição Electrónicos  3-Channel Digital
PDF  84 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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ADP1053ACPZ-R7 Folha de dados(HTML) 77 Page - Analog Devices

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Data Sheet
ADP1053
Rev. A | Page 77 of 84
CUSTOMIZED REGISTERS
Table 123. Register 0xFE82—Custom Register
Bits
Bit Name
R/W
Description
[7:0]
Custom register
R/W
This register is available to the user to store custom information. For example, this register can
be used to store user software or hardware revision information.
Table 124. Register 0xFE83—REVERSE_A/REVERSE_B Flag Configuration
Bits
Bit Name
R/W
Description
These bits specify the action to take when the REVERSE_B flag is set.
Bit 7
Bit 6
Flag Action
0
0
None
0
1
Disable PWM outputs in Channel A
1
0
Disable PWM outputs in Channel B
[7:6]
REVERSE_B flag
action
R/W
1
1
Disable all PWM outputs (Channel A, Channel B, and Channel C)
R/W
These bits specify the action to take after the REVERSE_B flag is cleared.
Bit 5
Bit 4
Action After Flag Is Cleared
0
0
After the reenable delay time, the PWM outputs are reenabled using the soft
start process
0
1
The PWM outputs are reenabled immediately without a soft start
1
0
A PSON signal is needed to reenable the PWM outputs
[5:4]
Action after
REVERSE_B flag
is cleared
1
1
A PSON signal is needed to reenable the PWM outputs
These bits specify the action to take when the REVERSE_A flag is set.
Bit 3
Bit 2
Flag Action
0
0
None
0
1
Disable PWM outputs in Channel A
1
0
Disable PWM outputs in Channel B
[3:2]
REVERSE_A flag
action
R/W
1
1
Disable all PWM outputs (Channel A, Channel B, and Channel C)
R/W
These bits specify the action to take after the REVERSE_A flag is cleared.
Bit 1
Bit 0
Action After Flag Is Cleared
0
0
After the reenable delay time, the PWM outputs are reenabled using the soft
start process
0
1
The PWM outputs are reenabled immediately without a soft start
1
0
A PSON signal is needed to reenable the PWM outputs
[1:0]
Action after
REVERSE_A flag
is cleared
1
1
A PSON signal is needed to reenable the PWM outputs
Table 125. Register 0xFE84 and Register 0xFE85—REVERSE_A/REVERSE_B Flag Settings
Bits
Bit Name
R/W
Description
[7:4]
Reserved
R/W
Reserved.
3
Debounce time
R/W
This bit sets the debounce time for the REVERSE_A and REVERSE_B flags.
0 = 40 ns.
1 = 200 ns.
These bits specify the CS2 reverse current protection threshold. When the CS2 negative current
falls below this threshold, the REVERSE_A or REVERSE_B flag is triggered.
Bit 2
Bit 1
Bit 0
Trigger Threshold
min (mV)
Trigger Threshold
Setting (mV)
Trigger Threshold
max (mV)
0
0
X
Reserved
0
1
0
−15.8
−10
−3.6
0
1
1
−19.4
−13
−6.6
1
0
0
−23.2
−17
−9.6
1
0
1
−27
−20
−12.4
1
1
0
−30.8
−24
−15.3
[2:0]
Reverse current
protection threshold
R/W
1
1
1
−34.7
−27
−18.1



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