ADIN1300CCPZ-R7 datasheet(20/96 Pages) AD

20 / 96 page

Data Sheet

ADIN1300

THEORY OF OPERATION

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Rev. B | 20 of 96

MAC INTERFACE

The ADIN1300 provides the option of RGMII, MII, or RMII MAC

interface. The MAC interface is selected using hardware configura-

tion pins (see Table 27) or via software.

RGMII Interface Mode

Figure 20. RGMII MAC-PHY Interface Signals

The RGMII interface is capable of supporting data rates of 1 Gbps,

100 Mbps, and 10 Mbps. For the receive interface, the ADIN1300

generates a 125 MHz, 25 MHz, or 2.5 MHz RXC signal to syn-

chronize the RXD_x pin receive data in 1000BASE-T, 100BASE-

TX, or 10BASE-Te modes, respectively. The RX_CTL is a combina-

tion of the RX_DV and RX_ER signals (as described in the MII

Interface Mode section) using both edges of the RXC signal. The

ADIN1300 transmits the RX_DV signal on the positive edge of RXC

and a combination (XOR function) of RX_DV and RX_ER on the

negative edge of RXC.

For the transmit interface, when operating in 1000BASE-T mode,

the MAC drives TXC with a 125 MHz clock signal. The MAC

transmits the TXD_x pin data, Bits[3:0] on the positive edge of

TXC, and TXD_x pin data, Bits[7:4] on the negative edge of TXC.

In 100BASE-TX and 10BASE-Te modes, TXC is at 25 MHz and

2.5 MHz, respectively, and the MAC transmits the TXD_x pin data,

Bits[3:0] on the rising edges of TXC (but in accordance with the

RGMII standard, the data may be duplicated on the falling edge of

the appropriate clock). TX_CTL is a combination of the TX_EN and

TX_ER signals using both edges of TXC. TX_EN is transmitted on

the positive edge of TXC, and TX_EN XOR TX_ER is transmitted

on the negative edge of TXC.

Due to the fact that data is transmitted on both edges of the clock,

an accurate delay requirement of 2 ns is required on both clock

edges (see Figure 21) to ensure that the delayed clock is at the

center of the data window, ensuring accurate data capture.

It is possible to enable this 2 ns delay on RXC only or on both

RXC and TXC using hardware pin configuration settings (see

Table 27). These delays can also be configured in software (see

GE_RGMII_CFG register). In Figure 21, the 8 ns period refers

to 1000BASE-T operation, which is 40 ns or 400 ns in the case

of 100BASE-TX and 10BASE-Te, respectively. The 2 ns delay is

valid for 10BASE-Te, 100BASE-TX, and 1000BASE-T. The RGMII

interface operates at 10 Mbps and 100 Mbps speeds exactly the

same way it does at Gigabit speed with the exception that the data

may be duplicated on the falling edge of the appropriate clock., (see

RGMII Interface Mode) shows similar timing for 100BASE-TX.

Figure 21. DLL Waveform (1000BASE-T)

Figure 22. DLL Waveform (100BASE-TX)

MII Interface Mode

Figure 23. MII MAC to PHY Interface Signals

The MII interface is capable of supporting data rates of 100 Mbps

and 10 Mbps. For the receive interface, the ADIN1300 generates a

25 MHz or 2.5 MHz RX_CLK signal to synchronize the RXD_x pin

receive data in 100BASE-TX or 10BASE-Te modes, respectively.

RX_DV indicates to the MAC that there is valid data present on

the RXD_x receive pin. RX_ER is driven high by the ADIN1300 if

an error is detected in the frame that was received from the MDI

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