ADIN1300CCPZ-R7 datasheet(89/96 Pages) AD

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Data Sheet

ADIN1300

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Rev. B | 89 of 96

Table 127. Bit Descriptions for GE_RGMII_CFG (Continued)

Bits

Bit Name

Description

Reset

Access

010: 7 × tU + 400 ps.

001: 6 × tU + 400 ps.

000: 8 × tU + 400 ps.

GE_RGMII_RX_ID_EN

Enable/disable receive clock internal 2 ns delay in RGMII mode. Note that the default value

of this bit is configurable via hardware configuration pins. This allows the default operation

of the PHY to be configured in unmanaged applications.

0x1

R/W

1: enable receive clock internal 2 ns delay in RGMII mode.

0: disable receive clock internal 2 ns delay in RGMII mode.

GE_RGMII_TX_ID_EN

Enable/disable transmit clock internal 2 ns delay in RGMII mode. Note that the default value

of this bit is configurable via hardware configuration pins. This allows the default operation

of the PHY to be configured in unmanaged applications.

0x1

R/W

1: enable transmit clock internal 2 ns delay in RGMII mode.

0: disable transmit clock internal 2 ns delay in RGMII mode.

GE_RGMII_EN

This bit selects the RGMII MAC interface mode. Note that the default value of this bit is

configurable via hardware configuration pins. This allows the default operation of the PHY

to be configured in unmanaged applications.

0x1

R/W

Subsystem RMII Configuration Register

Address: 0xFF24, Reset: 0x0116, Name: GE_RMII_CFG

This register allows the MAC interface RMII configuration to be controlled.

Table 128. Bit Descriptions for GE_RMII_CFG

Bits

Bit Name

Description

Reset

Access

[15:8]

RESERVED

Reserved.

0x1

GE_RMII_FIFO_RST

This bit allows the RMII FIFO to be reset.

0x0

R/W

[6:4]

GE_RMII_FIFO_DPTH

This field allows the RMII receive FIFO depth to be selected.

0x1

R/W

111: reserved.

110: reserved.

101: ± 24 bits.

100: ± 20 bits.

011: ± 16 bits.

010: ± 12 bits.

001: ± 8 bits.

000: ± 4 bits.

GE_RMII_TXD_CHK_EN

This bit determines whether or not the TXD_0 pin and TXD_1 pin are monitored to detect the

start of a frame. This bit allows connecting the RMII receive CRS_DV to the RMII TX_EN signal.

This allows a receive to transmit RMII pin loopback for media converter applications. This is

something that it is not supported in the RMII specification.

0x0

R/W

GE_RMII_CRS_EN

This bit determines whether or not CRS is encoded in the CRS_DV output signal. This allows a

receive to transmit RMII pin loopback for media converter applications. This is something that it

is not supported in the RMII specification.

0x1

R/W

GE_RMII_BAD_SSD_RX_ER_EN

This bit determines whether or not the RX_ER output signal is asserted when a false carrier

(bad SSD) is detected. When cleared, RX_ER is only asserted in case of a symbol error during

a frame.

0x1

R/W

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