ADIN1300CCPZ-R7 datasheet(78/96 Pages) AD

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Data Sheet

ADIN1300

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Rev. B | 78 of 96

Table 97. Bit Descriptions for FIFO_SYNC (Continued)

Bits

Bit Name

Description

Reset

Access

FIFO_SYNC

FIFO_SYNC. When set, the transmit FIFO is configured for synchronous operation (except in 1000BASE-T slave mode)

to minimize latency.

0x0

R/W

Start of Packet Control Register

Address: 0x9428, Reset: 0x0034, Name: SOP_CTRL

This register controls the start of packet (SOP) detection for IEEE 1588 time stamp controls.

Table 98. Bit Descriptions for SOP_CTRL

Bits

Bit Name

Description

Reset

Access

[15:7]

RESERVED

Reserved.

0x0

[6:4]

SOP_N_8_CYCM_1

When the SOP_NCYC_EN bit is set, the SOP_N_8_CYCM_1 bit field specifies the number of cycles of the

MII RX_CLK clock that the transmit and receive SOP indications remain asserted. Add 1 to the value specified

and then multiply by 8 to get the number of cycles. Note that the SOP indications are always deasserted at the

end of the frame.

0x3

R/W

SOP_NCYC_EN

When this bit is set, the duration of the transmit and receive SOP indications are defined by the

SOP_N_8_CYCM_1 bit field. Otherwise, the SOP indications are set for the duration of the frame.

0x0

R/W

SOP_SFD_EN

When this bit is set, SFD detection is enabled, so that the SOP signals are asserted when the SFD in the

frame is detected. If this register bit is cleared, the SOP signals are asserted on the first byte or nibble of the

frame. Note that if this signal is changed while packets are being transmitted or received, the SOP signals

may be wrongly asserted. Therefore, only change the signal while the link is down or when SOP_TX_EN and

SOP_RX_EN are cleared.

0x1

R/W

SOP_RX_EN

When set, this bit enables the generation of SOP detection for received frames.

0x0

R/W

SOP_TX_EN

When set, this bit enables the generation of SOP detection for transmitted frames. To minimize the SOP

indication variation, the detection is done after the transmit FIFO for modes in which the transmit FIFO is used.

0x0

R/W

Start of Packet Receive Detection Delay Register

Address: 0x9429, Reset: 0x0000, Name: SOP_RX_DEL

This register controls the receive side SOP detection delay.

Table 99. Bit Descriptions for SOP_RX_DEL

Bits

Bit Name

Description

Reset

Access

[15:11]

SOP_RX_10_DEL_NCYC

This bit field specifies the number of cycles of the MII RX_CLK clock to delay the received frames

SOP indication for 10BASE-T links.

0x0

R/W

[10:6]

SOP_RX_100_DEL_NCYC

This bit field specifies the number of cycles of the MII RX_CLK clock to delay the received frames

SOP indication for 100BASE-TX links.

0x0

R/W

[5:0]

SOP_RX_1000_DEL_NCYC

This register field specifies the number of cycles of the receive clock (for example, 8 ns cycles) to

delay the received frames SOP indication for 1000BASE-T links. It is mainly intended to support

MAC interfaces with long latency in Gigabit mode so that the received frame SOP indication is not

asserted before the MAC receives the frame.

0x0

R/W

Start of Packet Transmit Detection Delay Register

Address: 0x942A, Reset: 0x0000, Name: SOP_TX_DEL

This register controls the transmit side SOP detection delay.

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