ADIN1300CCPZ-R7 datasheet(52/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 52 of 96

Table 35. Bit Descriptions for PHY_ID_1

Bits

Bit Name

Description

Reset

Access

[15:0]

PHY_ID_1

Organizationally Unique Identifier Bits[3:18].

0x283

PHY Identifier 2 Register

Address: 0x0003, Reset: 0xBC30, Name: PHY_ID_2

This address corresponds to the MII status register specified in Clause 22.2.4.3.1 of IEEE Standard 802.3 and allows 6 bits of the OUI along

with the model number and revision number to be observed.

Table 36. Bit Descriptions for PHY_ID_2

Bits

Bit Name

Description

Reset

Access

[15:10]

PHY_ID_2_OUI

Organizationally Unique Identifier Bits[19:24].

0x2F

[9:4]

MODEL_NUM

Manufacturer Model Number.

0x3

[3:0]

REV_NUM

Manufacturer Revision Number.

0x0

Autonegotiation Advertisement Register

Address: 0x0004, Reset: 0x01E1, Name: AUTONEG_ADV

This address corresponds to the autonegotiation advertisement register specified in Clause 28.2.4.1.3 of IEEE Standard 802.3. Note that the

default reset value of this register is dependent on the hardware configuration pins settings.

Table 37. Bit Descriptions for AUTONEG_ADV

Bits

Bit Name

Description

Reset

Access

NEXT_PAGE_ADV

Next page exchange occurs after the base link codewords have been exchanged. Next page exchange

consists of using the normal autonegotiation arbitration process to send next page messages. Next page

transmission ends when both ends of a link segment set their next page bits to Logic 0, indicating that

neither has anything additional to transmit.

0x0

R/W

RESERVED

Reserved.

0x0

REM_FLT_ADV

The remote fault bit provides a standard transport mechanism for the transmission of simple fault

information.

0x0

R/W

EXT_NEXT_PAGE_ADV

The extended next page bit indicates that the local device supports transmission of extended next pages.

The use of extended next page is orthogonal to the negotiated data rate, medium, or link technology.

0x0

R/W

APAUSE_ADV

The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information

indicating supported technologies specific to the selector field value. This bit is to advertise asymmetric

pause operation for full duplex links.

0x0

R/W

PAUSE_ADV

The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information

indicating supported technologies specific to the selector field value. This bit is to advertise pause operation

for full duplex links.

0x0

R/W

T_4_ADV

The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information

indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-T4

and always reads as 1'b0 because this technology is not supported.

0x0

FD_100_ADV

The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information

indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-TX

full duplex. Note that the default value of this register bit is configurable via the hardware configuration pins,

which allows the default operation of the PHY to be configured in unmanaged applications.

0x1

R/W

HD_100_ADV

The technology ability field is a 7-bit wide field (Bits[11:5] within this register) containing information

indicating supported technologies specific to the selector field value. This bit is to advertise 100BASE-TX

0x1

R/W

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