ADIN1300CCPZ-R7 datasheet(37/96 Pages) AD

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Data Sheet

ADIN1300

ON-CHIP DIAGNOSTICS

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Rev. B | 37 of 96

CABLE DIAGNOSTICS

The ADIN1300 has on-chip cable diagnostics capabilities. This

cable analysis can be used to detect cable impairments that may

be preventing the establishment of a Gigabit link or degrading

performance and can be performed both when the link is up or

when the link is down.

Cable Length Estimate

Each time a 100BASE-TX or 1000BASE-T link is brought up, the

ADIN1300 reports an estimate (typically ±15m) of the cable length

based on the signal processing. This can be read in the cable

diagnostics cable length estimate register (CDIAG_CBL_LEN_EST

10BASE-Te link.

Cable Analysis with TDR

When the link is down, the ADIN1300 can run cable fault detection

using time domain reflectometry (TDR). By transmitting pulses and

analyzing the reflections, the PHY can detect cable faults like

opens, shorts, cross pair shorts, and the distance to the nearest

fault. The PHY can also determine that the pair is well terminated

and does not have any faults.

Put the remote PHY in a power-down state or disconnect the PHY

to run cable fault detection because remote PHY link pulses can

interfere with the analysis of the reflected pulses and can return

a pair busy result. TDR measurements provide a more accurate

cable length (typically ±2m) than the signal analysis method used in

the cable length estimate described in the Cable Length Estimate

section.

The cable fault detection is automatically run on all four pairs

looking at all combinations of pair faults by first putting the

PHY in standby (clear the LINK_EN bit, PHY_CTRL_3 register,

Address 0x0017) and then enabling the diagnostic clock (set the

DIAG_CLK_EN bit, PHY_CTRL_1 register, Address 0x0012). Ca-

ble diagnostics can then be run (set the CDIAG_RUN bit in the

CDIAG_RUN register, Address 0xBA1B).

The results are reported for each pair in the cable diagnostics re-

sults registers, CDIAG_DTLD_RSLTS_0, CDIAG_DTLD_RSLTS_1,

CDIAG_DTLD_RSLTS_2, and CDIAG_DTLD_RSLTS_3, Address

0xBA1D to Address 0xBA20. The distance to the first fault

for each pair is reported in the cable fault distance registers,

CDIAG_FLT_DIST_0, CDIAG_FLT_DIST_1, CDIAG_FLT_DIST_2,

and CDIAG_FLT_DIST_3, Address 0xBA21 to Address 0xBA24.

Cable Polarity Inversion, Pair Swaps

A polarity inversion on each pair is reported in the polarity in-

version register bits (PHY_2_STATUS register, Address 0x001F,

Bits[13:10]) and the B_10_POL_INV bit (PHY_STATUS_1 register,

Address 0x001A). Pair swaps are reported in the pair swap register

bits (PAIR_23_SWAP bit, Address 0x001F and PAIR_01_SWAP bit,

Address 0x001A).

Cable Signal Quality, MSE

The ADIN1300 provides a measure of the signal quality of the

established link. This measurement relates directly to the signal-to-

noise ratio (SNR) seen by the PHY receiver.

When the link is up, the signal quality on each pair is indicat-

ed in the mean square error register for each pair (MSE_A,

MSE_B, MSE_C, and MSE_D registers, Address 0x8402 to Ad-

dress 0x8405, Bits[7:0]). MSE register values in the range of 3 to 5

are expected for a cable length of up to 100 meters. As the cable

length becomes longer and external noise increases, the mean

square error (MSE) reported increases.

To calculate the associated signal-to-noise ratio during idle mode,

apply the following formula to the MSE value read:

SNR (dB) = 10 × log10(MSE/1024)

(1)

An SNR value > 21 dB (MSE of 8 or 9) indicates essentially error

free performance. At 18 dB or 19 dB (MSE of 13 or 14), occasional

errors may be observed over a 24-hour period.

ENHANCED LINK DETECTION

The ADIN1300 supports enhanced link detection, which is early

detection and indication of link loss. This is a feature where the

received signal is monitored, and if a significant number of consec-

utive samples of the signal are not as expected, early indication of

link down is indicated. The ADIN1300 can simultaneously monitor

for a significant number of consecutive 0s, a significant number

of consecutive 1s, or a significant number of consecutive invalid

levels.

If enhanced link detection is enabled (it is enabled by default),

the ADIN1300 typically reacts to a break in the cable within 10

μs and indicates link down via the LINK_ST pin. If enhanced link

detection is not enabled, the ADIN1300 follows the IEEE standard,

and in 100BASE-TX, it can take more than either 350 ms or 750

ms in 1000BASE-T, depending if the PHY is 1000BASE-T master or

1000BASE-T slave.

Enhanced link detection is enabled by default. To change the

configuration for 100BASE-TX via the enhanced link detection

100BASE-TX enable register bits (FLD_EN register, Address

0x8E27, Bit 5 and Bit 3) and for 1000BASE-T via the 1000BASE-T

enhanced link detection enable register bits (FLD_EN register,

Address 0x8E27, Bit 4, Bit 2, and Bit 0).

Do not enable 1000BASE-T retrain (clear the B_1000_RTRN_EN

bit, Address 0xA001) if enhanced link detection is enabled for

1000BASE-T.

The latched status of the enhanced link detection function can

be read via the enhanced link detection status bit, FAST_

LINK_DOWN_LAT (Address 0x8E38).

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