ADIN1300CCPZ-R7 datasheet(25/96 Pages) AD

25 / 96 page

Data Sheet

ADIN1300

THEORY OF OPERATION

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Rev. B | 25 of 96

►

The selected PHY output clock (if enabled) is available on the

GP_CLK pin during this reset.

PHY Core Software Reset

The PHY core registers can be reset by setting the SFT_RST bit

in the MII_CONTROL register, Address 0x0000 to 1. This bit is self

clearing. Setting this bit resets the PHY core registers, the MAC

interface block, and the PHY core. The hardware configuration

pins are not reread, and previously latched values of the hardware

configuration pins are used to set the default values of the pin

dependent registers in the PHY core registers. The subsystem

registers are not reset to default values. This is a useful way to

reset the PHY core registers to a known configuration defined by

software without resetting the rest of the ADIN1300 circuitry.

The following events occur after a PHY core software reset:

►

The crystal oscillator circuit is not disabled during this type of

reset.

►

The hardware configuration pins are not reread. The pin depend-

ent registers in PHY core registers are reset to the default

values defined by the previously latched values of the hardware

configuration pins. The subsystem registers are not reset to their

default values.

►

The MAC interface block is not reset.

►

The PHY core is reset.

►

If a 125 MHz clock is selected as the PHY output clock, the

GP_CLK pin, the PHY core CMU is not reset. Otherwise, the

CMU is reset.

►

The reference clock (if enabled) is available on the CLK25_REF

pin during this reset.

►

The selected PHY output clock (if enabled) is available on the

GP_CLK pin during this reset.

Table 20. ADIN1300 Reset Options Summary

Reset Type

Hardware Pin

Configuration Values

Latched Following

Reset

Subsystem

Registers

Reset

PHY Core

Registers

Reset

MAC

Interface

Block Reset

XTAL Oscillator

Disabled

During Reset

CLK25_REF (if

Enabled)

Available During

Reset

GP_CLK Output

(if Enabled)

Available

During Reset

Hardware Reset

Yes

Subsystem Software Reset

with Pin Configuration

Yes

Subsystem Software Reset No

Yes

PHY Core Software Reset

Yes

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