ADIN1300CCPZ-R7 datasheet(91/96 Pages) AD

91 / 96 page

Data Sheet

ADIN1300

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Rev. B | 91 of 96

Subsystem 10BASE-T Preamble Generation Register

Address: 0xFF38, Reset: 0x0000, Name: GE_B10_REGEN_PRE

In normal operation, the 10BASE-T preamble is consumed while synchronizing 10BASE-T receive timing and only 1 byte or 2 bytes of

preamble are sent to the MAC. Setting this bit causes the GE subsystem to regenerate a full 10BASE-T preamble.

Table 131. Bit Descriptions for GE_PHY_IF_CFG

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

GE_B10_REGEN_PRE

Setting this bit causes the GE subsystem to regenerate a full 10BASE-T preamble. This field must always

be left at the default value of 0x0 for general use and set to 0x1 for media converter applications.

0x0

R/W

Subsystem RGMII I/O Control Register

Address: 0xFF3A, Reset: 0x0005, Name: GE_RGMII_IO_CNTRL

This register allows the characteristics of the RGMII I/O cells to be

controlled.

Table 132. Bit Descriptions for GE_RGMII_IO_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:4]

RESERVED

Reserved.

0x0

[3:2]

GE_RGMII_RX_DRV

This bit field allows the drive strength of the RGMII receive buffers to be modified. Lower values correspond

to higher drive current.

0x1

R/W

[1:0]

RESERVED

Reserved.

0x1

R/W

Subsystem Clock I/O Control Register

Address: 0xFF3B, Reset: 0x0002, Name: GE_CLK_IO_CNTRL

This register allows the characteristics of the clock I/O cells to be controlled.

Table 133. Bit Descriptions for GE_CLK_IO_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:3]

RESERVED

Reserved.

0x0

[2:1]

GE_CLK_DRV This bit field allows the drive strength of the clock buffers (and LINK_ST) to be modified. Lower values correspond to

higher drive current.

0x1

R/W

RESERVED

Reserved.

0x0

R/W

Subsystem Link Status Invert Enable Register

Address: 0xFF3C, Reset: 0x0000, Name: GE_LNK_STAT_INV_EN

This register allows the link status output signal on the LINK_ST pin to be inverted, meaning that link up is indicated by setting LINK_ST low.

Table 134. Bit Descriptions for GE_LNK_STAT_INV_EN

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

GE_LNK_STAT_INV_EN

When set to 1, this bit enables the link status output signal on the LINK_ST pin to be inverted, meaning

that link up is indicated by setting LINK_ST low.

0x0

R/W

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