ADIN1300CCPZ-R7 datasheet(50/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 50 of 96

Table 33. Bit Descriptions for MII_CONTROL (Continued)

Bits

Bit Name

Description

Reset

Access

SPEED_SEL_LSB

The speed selection MSB and LSB register bits are used to configure the link speed. Note that the default value of

this register bit is configurable via the hardware configuration pins. This allows the default operation of the PHY to

be configured in unmanaged applications.

0x0

R/W

11: reserved.

10: 1 Gbps.

01: 100 Mbps.

00: 10 Mbps.

AUTONEG_EN

The autonegotiation enable bit is used to enable/disable autonegotiation. Note that the default value of this

configured in unmanaged applications.

0x1

R/W

1: enable autonegotiation process.

0: disable autonegotiation process.

SFT_PD

Software Power-Down Bit. Note that the default value of this register bit is configurable via the hardware

configuration pins. The PHY can be held in reset until initialized by the software.

0x0

R/W

1: software power-down.

0: normal operation.

ISOLATE

Isolate Bit.

0x0

R/W

1: electrically isolate PHY from MAC interface by setting MAC interface pins to tristate (even if active).

0: normal operation.

RESTART_ANEG

Restart Autonegotiation Bit. Note that this bit is self clearing. When the autonegotiation process is restarted, this bit

returns to 1'b0.

0x0

R/W SC

1: restart the autonegotiation process.

0: normal operation.

DPLX_MODE

Duplex Mode Bit.

0x0

R/W

1: full duplex.

0: half duplex.

COLTEST

Collision Test Bit.

0x0

R/W

1: enable collision signal test.

0: disable collision signal test.

SPEED_SEL_MSB

See SPEED_SEL_LSB Bit Description.

0x1

R/W

11: reserved.

10: 1 Gbps.

01: 100 Mbps.

00: 10 Mbps.

UNIDIR_EN

The unidirectional enable register bit is read only and always reads as 1'b0. Transmission from the media

independent interface is only enabled when the PHY has determined that a valid link has been established.

0x0

[4:0]

RESERVED

Reserved.

0x0

MII Status Register

Address: 0x0001, Reset: 0x7949, Name: MII_STATUS

This address corresponds to the MII status register specified in Clause 22.2.4.2 of IEEE Standard 802.3.

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