ADIN1300CCPZ-R7 datasheet(62/96 Pages) AD

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Data Sheet

ADIN1300

analog.com

Rev. B | 62 of 96

Table 54. Bit Descriptions for IRQ_MASK (Continued)

Bits

Bit Name

Description

Reset

Access

0: disable frame checker/generator interrupt

PAGE_RX_IRQ_EN

Autonegotiation Page Received Interrupt Enable Bit.

0x0

R/W

1: enable autonegotiation page received interrupt.

0: disable autonegotiation page received interrupt.

IDLE_ERR_CNT_IRQ_EN

Idle Error Counter Saturated Interrupt Enable Bit.

0x0

R/W

1: enable idle error counter saturated interrupt.

0: disable idle error counter saturated interrupt.

FIFO_OU_IRQ_EN

MAC Interface FIFO Overflow/Underflow Interrupt Enable Bit.

0x0

R/W

1: enable MAC interface FIFO overflow/underflow interrupt.

0: disable MAC interface FIFO overflow/underflow interrupt.

RX_STAT_CHNG_IRQ_EN

Receive Status Changed Interrupt Enable Bit.

0x0

R/W

1: enable receive status changed interrupt.

0: disable receive status changed interrupt.

LNK_STAT_CHNG_IRQ_EN

Link Status Changed Interrupt Enable Bit.

0x0

R/W

1: enable link status changed interrupt.

0: disable link status changed interrupt.

SPEED_CHNG_IRQ_EN

Speed Changed Interrupt Enable Bit.

0x0

R/W

1: enable speed changed interrupt.

0: disable speed changed interrupt.

HW_IRQ_EN

When set, this enables the hardware interrupt pin, INT_N, and INT_N is asserted when an interrupt

is generated.

0x0

R/W

1: enable the hardware interrupt pin, INT_N.

0: disable the hardware interrupt pin, INT_N.

Interrupt Status Register

Address: 0x0019, Reset: 0x0000, Name: IRQ_STATUS

The interrupt status register is used to check which interrupts have triggered since the last time it was read. Each bit goes high when the

associated interrupt triggers and then latches high until it is unlatched by reading (note that reading any of the bits in this register unlatches all

of the bits in the register). The bits of IRQ_STATUS go high even when the associated interrupts are not enabled. However, only bits associated

with enabled interrupts are considered when generating the IRQ_PENDING indication.

Table 55. Bit Descriptions for IRQ_STATUS

Bits

Bit Name

Description

Reset

Access

[15:11]

RESERVED

Reserved.

0x0

CBL_DIAG_IRQ_STAT

If the cable diagnostics interrupt status bit is 1, this indicates that the associated interrupt

triggered since last read. Note that when this bit goes high, it latches high until it is unlatched by

reading.

0x0

R LH

MDIO_SYNC_IRQ_STAT

If the MDIO synchronization lost interrupt status bit is 1, this indicates that the associated

interrupt triggered since last read. Note that when this bit goes high, it latches high until it is

unlatched by reading.

0x0

R LH

AN_STAT_CHNG_IRQ_STAT

If the autonegotiation status changed interrupt status bit is 1, this indicates that the associated

interrupt triggered since last read. Note that when this bit goes high, it latches high until it is

unlatched by reading.

0x0

R LH

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