ADIN1300CCPZ-R7 datasheet(28/96 Pages) AD

28 / 96 page

Data Sheet

ADIN1300

THEORY OF OPERATION

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Rev. B | 28 of 96

LINK STATUS, LINK_ST

The LINK_ST pin is a general-purpose output used to indicate to

the MAC whether a valid link has been established. LINK_ST is

active high by default (this setting can be changed by software,

by writing to the GE_LNK_STAT_INV_EN register). For applications

requiring a second LED, the LINK_ST pin must be used. The

default drive current for this pin is 8 mA, and it can be increased by

writing to the GE_CLK_IO_CNTRL register bit field, GE_CLK_DRV,

if the application requires the LINK_ST pin to drive an LED directly.

LINK_ST is referenced to the VDDIO domain and is used for

hardware strapping (PHY_CFG1). A level shifter may be required

when VDDIO is running at a lower voltage.

PHY OUTPUT CLOCKS

The following internal PHY clock signals can be made available at

the GP_CLK pin:

►

125 MHz free running clock

►

125 MHz recovered clock

►

25 MHz clock

►

25 MHz or 125 MHz free running clock

►

25 MHz or 125 MHz recovered clock

This is configured in through register writes via the GE_CLK_CFG

selecting the 125 MHz free running clock has an impact on power

consumption, as the CMU is always powered up except during

reset and power up.

POWER SUPPLY DOMAINS

The ADIN1300 has the following three power supply domains and

requires a minimum of two supply sources, 0.9 V and 3.3 V:

►

DVDD_0P9 is the 0.9 V digital core power supply input.

►

AVDD_3P3 is the 3.3 V analog power supply input for the PHY

MDI interface, analog circuitry, XTAL oscillator, DLL, RESET_N,

CLK25_REF generation, and LED circuitry.

►

VDDIO enables the MDIO and MAC interface voltage supply

to be configured independently of the other circuitry on the

ADIN1300. In most cases, RMII/MII is operated at 3.3 V and

RGMII is operated at 2.5 V, but the MAC interface can operate at

3.3 V, 2.5 V, or 1.8 V to allow the MAC interface to run at a lower

voltage and power if the MAC supports this.

There are no power supply sequencing requirements around the

order of power being applied to the device. See the Power-Up

Timing section for more details.

Figure 27. PHY Output Clocks Simplified Diagram

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