ADIN1300CCPZ-R7 datasheet(94/96 Pages) AD

94 / 96 page

Data Sheet

ADIN1300

PCB LAYOUT RECOMMENDATIONS

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Rev. B | 94 of 96

This is an overview of the key areas of interest during placement

and layout of the PHY and corresponding support components.

Take care when routing high speed interface signals to maximize

signal performance and ensure optimum EMC performance, with a

view to ensure critical signal traces are kept as short as possible to

minimize noise coupling.

PHY PACKAGE LAYOUT

The LFCSP has an exposed pad underneath the package that

must be soldered to the PCB ground for mechanical and thermal

reasons. For thermal impedance performance and to maximize

heat removal, use of a 4 × 4 array of thermal vias beneath the

exposed ground pad is recommended.

There are also two bus bars on either side of the exposed pad.

These bus bars are connected to internal voltage rails and are

not intended to be, and must not be soldered to the board. The

PCB land pattern must incorporate the exposed ground paddle with

vias and these two keep out areas around the bus bars in the

footprint. No PCB traces or vias can be used in either of the keep

out areas. The EVAL-ADIN1300FMCZ uses an array of 4 × 4 vias

on a 0.75 mm grid arrangement, as shown in Figure 45. The via

pad diameter dimension is 0.02 in. (0.5015 mm) and the finished

drill hole diameter is 0.01 in. (0.2489 mm).

Figure 45. Exposed Paddle Via Array on EVAL-ADIN1300FMCZ

COMPONENT PLACEMENT

Prioritization of the critical traces and components helps simplify

the routing exercise. Place and orient the critical traces and compo-

nents first to ensure an effective layout with minimal turns, vias,

and crossing traces. For an Ethernet PHY layout, the important

components are the crystal and load capacitors, the transformer

on the MDI lines, and all bypass capacitors local to the device.

Prioritize these components and the routing to them. Keep the PHY

chip at least 1 in. away from the edge of the board. The following

sections provide more detail for each of the areas.

Crystal Placement and Routing

To ensure minimum current consumption and to minimize stray

capacitances, make connections between the crystal, capacitors,

and ground as close to the ADIN1300 as possible. For optimal

performance, the crystal and capacitors must be on the same side

of the board as the ADIN1300, with a solid ground plane under the

crystal and capacitors.

Magnetics Placement

Orient the magnetics and RJ45 in line with the MDI_x_x pins from

the PHY chip.

MDI, DIFFERENTIAL PAIR ROUTING

The MDI interface runs from the ADIN1300 PHY to the transformer,

and from there to the RJ45 connector. Traces running from the

MDI_x_x pins of the ADIN1300 to the magnetics must be on the

same side of the board, kept as short as possible (ideally less

than 1 in. in length), and individual trace impedance of these tracks

kept below 50 Ω, with differential impedance of 100 Ω for each

pair. The same recommendations apply for traces running from

the magnetics to the RJ45 connector. Keep impedances constant

throughout because any discontinuities may affect signal integrity.

Each pair must be routed together, trace widths kept the same

throughout, trace lengths kept equal where possible, and avoid any

right angles on these traces (use curves in traces or 45° angles).

Avoid stubs on all signal traces. Where possible, route traces on

the same layer.

Route traces over a continuous reference plane with no interrup-

tions to reduce inductance.

Where possible, ensure a solid return path underneath all signal

traces. Avoid routing signal traces across plane splits.

Figure 46. Things to Avoid when Routing Differential Pairs

MAC INTERFACE PINS

All signals within the transmit group must be length matched and

similarly for all signals within the receive group. Where possible,

route these interface pins on the same side as the component

pins. Keep trace lengths as short as possible. Route traces with an

impedance of 50 Ω to ground.

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