ST6373 datasheet(51/64 Pages) STMICROELECTRONICS

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ST6373

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SERIAL PERIPHERAL INTERFACE (Cont’d)

SCL Latch And Ddc2b Address Control Regis-

ter (SLACR)

Address: F3h - Read/Write

Reset Value: 40h

b7 to b4: Not used

b3: HSAE:

Hardware Slave Address Enable. This

bit allows the Slave I2C to check, after a Start Con-

dition Detection, both the Address A0/A1h for

DDC2B and the Programmed Address for the

switch to DDC2AB.

Note that software address contained in SSDR is

always valid.

0=Disable, 1=Enable, Write only, 1 after Reset

b2: SCLFLAG:

SCL FLAG bit. This bit is set on

SCL rising or falling edge according to the polarity

bit SCLEDGE. This flag can be reset by writing a 1

in SCLFLAG bit (Read and Reset, undefined after

reset).

b1: SCLITEN:

SCL INterrupt ENable bit.If this bit

is set an interrupt on vector # 3 is generated when

the SCL flag is set (Write Only, 0 after Reset).

b0: SCLEDGE:

SCL EDGE selection bit.The SCL

input latch is activated on either the positive or

negative edge of SCL line: if SCLEDGE is high the

latch will be triggered on the rising edge of SCL; if

this bit is low the latch will be triggered on the fall-

ing edge (Write Only, 0 after Reset).

Remark: In DDC1, it is not necessary to use the

SCL latch interrupt because the DDC1 SCL Falling

edge interrupt can be activated (see DDC1 mode).

4.8 MIRROR REGISTER

This is an 8-bits Register at address D9h. It is

cleared on Reset. After writing, the read value is

the reversed byte:

Bit0 -> Bit7, Bit1 -> Bit6, Bit2 -> Bit5, Bit3 -> Bit4,

Bit4 -> Bit3, Bit5 -> Bit2, Bit6 -> Bit1, Bit7 -> Bit0

4.9 XOR REGISTER

This is a 8-bit Register at address F4h. It is cleared

on Reset. After writing, the new content value is

the previous content ”XORed” with the written val-

ue.

To reset this register the user must read its con-

tents and rewrite it (A XOR A = 0).

HSAE

SCL

FLAG

SCL

ITEN

SCL

EDGE

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