ST6373 datasheet(50/64 Pages) STMICROELECTRONICS

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ST6373

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SERIAL PERIPHERAL INTERFACE (Cont’d)

TRS. Transmission/Reception Selection.

0 = Select Reception operation

1 = Select Transmission operation

Write Only.

This bit is also used in reading as a STOP Condi-

tion Detection Flag.

Read Only.

VSDAF. Verification of SDA line Flag. This bit is

set as soon as the data on SDA line is different to

the data inside SSDR, mainly in transmission but

also during the slave address reception when the

SLAVE mode is selected. [I

2C BUS ONLY]

0 = no difference detected

1 = Difference found on SDA

Read Only.

NADF. No Acknowledge Detection Flag. [I2CBUS

ONLY]

0 = Detection Acknowledge

1 = No Detection of Acknowledge

Read Only.

SBOR. SPI Byte Operation (Transmission or Re-

ception). This bit is set to start an operation; in I

SLAVE mode it is automatically set when a Start

Condition is detected.

0 = No Operation

1 = Operation Start

Read and Set.

Note that NO bit operation instructions are possi-

ble on this register.

SPI Serial Data Register (SSDR)

DDC

Address: CCh - Read/Write

Reset Value: XXh

I C

Address: CBh - Read/Write

Reset Value: XXh

SD7-SD0. Data bits, R/W, Undefined after Reset.

This Serial Data Register is composed of one Buff-

er Register and one Data Shift Register. When

AUTO = 1, the Shift Register is linked to the 128

byte DDC EEPROM dedicated to DDC1 and

DDC2B. The data will then automatically be sent

without CPU operation. The 128 bytes DDC EEP-

ROM can be addressed (programmed or read) by

the software only when bit AUTO = 0. Software

can address the buffer and not the Shift Register.

- The data transfer from the Shift Register to the

Buffer is always done at the end of a normal recep-

tion (TRS = 0) before the reset of SBOR. The buff-

er should not be read by the software during the

data transfer.

- With the DDC SPI, the loading of the Shift Regis-

ter is done in two different ways depending on the

AUTO bit:

When AUTO = 0 the transfer is done from the Buff-

er to the Shift Register on the setting of SBOR (or

also in I

2C SLAVE mode, on a Start Condition De-

tection).

When AUTO = 1, the transfer is done from the

DDC EEPROM to the Shift Register at the end of

each byte transmission. (The first byte is loaded

when SBOR is set simultaneously with AUTO)

Note:

When SBOR = 1, the loading of the Buffer does

not affect the Shift Register.

Auto-counter Register (ACR)

Address: F2h - Read/Write

Reset Value: 00h

b7: Not used

b6 to b0: 7 bits Auto-Counter, Read/Write, 00h af-

ter Reset.

Through these 7 bits the DDC1/DDC2B Address

Generator can be set at any EEPROM Start Ad-

dress from 00h to 7Fh. The content of the counter

can be read at any time during the DDC1 or

DDC2B Automatic Mode.

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

D5D4D3

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