ST6373 datasheet(44/64 Pages) STMICROELECTRONICS

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ST6373

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4.5 14-BIT PWM D/A CONVERTER

The PWM D/A CONVERTER (HDA) is composed

of a 14-bit counter that allows the conversion of

the digital content in an analog voltage, available

at the HDA output pin, by using Pulse Width Mod-

ification (PWM), and Bit Rate Multiplier (BRM)

techniques.

The tuning word consists of a 14-bit word con-

tained in the registers HDADATA1 (location EEh)

and HDADATA2 (location EFh). Coarse tuning

(PWM) is performed using the seven MSBs, while

fine tuning (BRM) is performed using the data in

the seven LSBits. With all zeros loaded the output

is zero; as the tuning voltage increases from all ze-

ros, the number of pulses in one period increase to

128 with all pulses being the same width. For val-

ues larger than 128, the PWM takes over and the

number of pulses in one period remains constant

at 128, but the width changes. At the other end of

the scale, when almost all ones are loaded, the

pulses will start to link together and the number of

pulses will decrease. When all ones are loaded,

the output will be almost 100% high but will have a

low pulse (1/16384 of the high pulse).

4.5.1 Output Details

Inside the on-chip D/A CONVERTER are included

the register latches, a reference counter, PWM

and BRM control circuitry. In the ST6373 the clock

for the 14-bit reference counter is 2MHz derived

from the 8MHz system clock. From the circuit point

of view, the seven most significant bits control the

coarse tuning, while the seven least significant bits

control the fine tuning. From the application and

software point of view, the 14 bits can be consid-

ered as one binary number.

As already mentioned the coarse tuning consists

of a PWM signal with 128 steps; we can consider

the fine tuning to cover 128 coarse tuning cycles.

The addition of pulses is described in the following

Table.

The HDA output pin has a standard drive push-pull

output configuration.

Table 12. Fine Tuning Pulse Addition

4.5.2 HDA Tuning Cell Registers

HDA Data Register 1 (HDAR1)

Address: EEh - Write only

Reset Value: XXh

D7-D0. These are the 8 least significant HDA data

bits. Bit 0 is the LSB. This register is undefined on

reset.

HDA Data Register 2 (HDAR2)

Address: EFh - Write only

Reset Value: XXh

D7-D6. These bits are not used.

D5-D0. These are the 6 most significant HDA data

bits. Bit 5 is the MSB. This register is undefined on

reset.

Fine Tunin g

(7 LSB)

° of pulses added at the

follo wing cycles

(0... 127)

0000001

0000010

32, 96

0000100

16, 48, 80, 112

0001000

8, 24, ....104, 120

0010000

4, 12, ....116, 124

0100000

2, 6, .... .122, 126

1000000

1, 3, .... .125, 127

HDA7

HDA6

HDA5

HDA4

HDA3

HDA2

HDA1

HDA0

HDA13 HDA12 HDA11 HDA10 HDA9

HDA8

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