ST6373 datasheet(24/64 Pages) STMICROELECTRONICS

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INTERRUPTS (Cont’d)

3.4.2 Interrupt Priority

The non-maskable interrupt request has the high-

est priority and can interrupt any other interrupt

routines at any time, nevertheless the other inter-

rupts cannot interrupt each other. If more than one

interrupt request is pending, they are processed

by the MCU Core according to their priority level:

vector #1 has the higher priority while vector #4

the lower. The priority of each interrupt source is

hardware fixed.

3.4.3 Interrupt Option Register

The Interrupt Option Register (IOR register, loca-

tion C8h) is used to enable/disable the individual

interrupt sources and to select the operating mode

of the external interrupt inputs. This register is ad-

dressed in the Data Space as a RAM location at

address C8h, nevertheless it is write-only register

that can not be accessed with single-bit opera-

tions. The operating modes of the external inter-

rupt inputs associated to interrupt vectors #1 and

#2 are selected through bits 4 and 5 of the IOR

Interrupt Option Register (IOR)

Address: (C8h) - Write only

Reset Value: XX00XXXXb

D7. Not used.

EL1. This is the Edge/Level selection bit of inter-

rupt #1. When set to one, the interrupt is generat-

ed on low level of the related signal; when cleared

to zero, the interrupt is generated on falling edge.

The bit is cleared to zero after reset.

ES2. This is the edge selection bit on interrupt #2.

This bit is used in ST6373 devices for VSYNC de-

tection, the interrupt for Timer 2 and the I

2CSPI. It

is cleared to zero on reset (falling edge), and must

be maintained at 0 if the Timer 2 and I

2C interrupts

are to be used. The VSYNC interrupt may be con-

figured to act on the falling edge (ES2=0) or rising

edge (ES2=1) according to the system design.

GEN. This is the global enable bit. When set to

one all interrupts are globally enabled; when this

bit is cleared to zero all interrupts are disabled (ex-

cluding NMI) independently to the individual inter-

rupt enable bit of each peripheral.

D3 - D0. These bits are not used.

NMI/PWR/VSync Interrupt Register (NPVIR)

b7: VSYNCST: (Read & Write, 0 written on Reset)

b6: VSYNCEN: (Read & Write, 0 written on Reset)

b5:PWRFLAG:(Read &Write, Undefined on Reset)

b4: PWINTEN: (Write Only, 0 written on Reset)

b3: PWREDGE: (Write Only, 0 written on Reset)

b2: NMIFLAG:(Read & Write, Undefined on Reset)

b1: NMINTEN: (Write Only, 0 written on Reset)

b0: NMIEDGE: (Write Only, 0 written on Reset)

Note that NO bit operation instructions are possible.

The input latch is activated on either the positive or

negative edge of the NMI (respectively PWRIN)

signal: if NMIEDGE (resp. PWREDGE) is high the

latch will be triggered on the rising edge of the sig-

nal at NMI (resp. PWRIN); if this bit is low the latch

will be triggered on the falling edge.

An interrupt can be generated if it is enabled: if

NMINTEN (resp. PWINTEN) is high, then the out-

put of the latch may generate an interrupt on vec-

tor #0 (resp. vector #4); if this bit is low the inter-

rupt is disabled.

The status of the latch is read with NMIFLAG (re-

sp. PWRFLAG): if NMIFLAG (resp. PWRFLAG) is

high, a signal has been latched. The latch can be

reset by setting NMIFLAG (resp. PWRFLAG).

The VSYNC input is linked to the interrupt vector #

2 through a latch.

If 1 is written in VSYNCST the latch will be trig-

gered on the rising edge of the signal at VSYNC, if

VSYNCST is low the latch will be triggered on the

falling edge (0 written on Reset).

An interrupt can be generated only if VSYNCEN is

at 1. Writing a 1 in VSYNCEN will also reset the

latch (0 written on Reset).

The status of the latch is read through the bit

VSYNCEN; reading a 1 means that a signal has

been latched.

The status of the VSYNC pin is read with the

VSYNCST bit.

EL1

ES2

GEN

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