ST6373 datasheet(47/64 Pages) STMICROELECTRONICS

47 / 64 page

ST6373

47/64

SERIAL PERIPHERAL INTERFACE (Cont’d)

4.7.1 SPI Modes

DDC1 Mode. In this mode, the eight bits of the

data register are shifted out of the register, most

significant bit first, clocked on the rising edge of

the VSYNC input. During the ninth period, the SDA

line remains high or low depending on the ACKC

bit. In Auto mode (AUTO=1), the 128 bytes of the

DDC EEPROM are sent in sequence until the

SCLD input goes low to indicate a DDC Acknowl-

edgment, an interrupt is generated and the trans-

fer is stopped. The data direction is from the MCU,

typically as data from the Monitor to the Host.

Slave Standard Shift Mode. The operation of this

mode is the same as the DDC1 Mode except that

the clock used is taken from the external clock in-

put (EXTCLK on PC3).

Master Standard Shift Mode. This mode corre-

sponds to the Standard Shift Protocol. Data in the

shift register is shifted out of the SDAD line at the

internal SPI clock speed after the transmission is

triggered. The synchronous clock for the data

transmission is output on the SCLD pin. An inter-

rupt can be generated at the end of transmission.

DDC2 or I2C Mode. This mode is used in conjunc-

tion with software to implement the I2C transmis-

sion protocol. In Master Mode, data written into the

data register (typically Address of the Slave and

the Read/Write (R/W) bit for I2C-bus) is shifted out

when triggered with a preceding Start Condition.

An Interrupt can be generated at the end of trans-

mission or this can be detected by polling. Arbitra-

tion is managed by comparing the data on the

SDAD line with the corresponding data bit of the

shift register and an error is flagged if they are dif-

ferent. If the addressed Slave stretches the low

period of the SCLD line, the Master is forced into a

wait state.In Slave Mode, the data register is load-

ed with its own slave address, and the DDC SPI

waits for detection of a START Condition. The ad-

dress received is compared to that set for the

slave, and if the address is correct, an acknowl-

edge is sent and an interrupt can be generated,

the SCLD line is held low to allow the software to

prepare for the incoming data. If the request in the

R/W bit is set (0) the external master wants to write

to the Slave, if reset, a data value is to be sent.

This is managed by the user software.

DDC2B Mode. The DDC2B mode follows the

DDC2 mode until a read command is received.

The SPI can then be programmed in AUTO mode

to send automatically the 128 bytes of the EEP-

ROM until the end of the communication.

2C SPI

The I2C SPI manages only the Standard Shift

SPI.

Figure 30. DDC1 Mode AUTO Not Set

VR02035

VSYNC

210

SDA

ACK

START

ST6373 Folha de dados(PDF) 47 Page - STMicroelectronics

ST6373 Folha de dados(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Folha de dados Download

Ligação URL