ST6373 datasheet(41/64 Pages) STMICROELECTRONICS

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ST6373

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SYNC PROCESSOR (Cont’d)

4.4.5 Video Blanking Generator

This block involves HFLY, VFLY inputs and

VSYNCO as input. The falling edges of HFLY (re-

spectively VFLY) are detected on the flag bit 4

(HFLYF) of PCBCR (respectively bit 5 (VFLYF)).

HFLY flag (respectively VFLY flag) is reset by soft-

ware writing zero.

The selection between PA5 and BLANK output is

done with bit 6 (BOS) of PCBCR;

SYNC Processor Control Register (SPCR)

Address: DFh - Read/Write

Reset Value: 00h

b7:

HVOS:

H/V

sync

Outputs

Selection

0=PA2/PA3

as normal port A configuration,

1=HsyncO instead of PA2, VsyncO instead of

PA3, Write Only, 0 at Reset.

Remark: H/VSyncO are forced to push-pull out-

puts

b6: HVGEN:

H/Vsync GENeration.

0= H/VsyncO <- H/VsyncI or H/VsyncIN (accord-

ing to H/VOPC)

1 = HsyncO <- HGEN: 62.5KHz, Pulse: 2

µs (posi-

tive polarity); VsyncO <- VGEN: 61Hz, Pulse: 64

µs

(positive polarity), Write Only, 0 at Reset.

b5: VOPC:

Vsync Output Polarity Control

0=Vsynco <- VsyncI, 1= Vsynco <- VsyncIN, Write

Only, 0 after Reset.

b4: HOPC:

Hsync Output Polarity Control

0=Hsynco <- HsyncI, 1=Hsynco<- HsyncIN, Write

Only, 0 after Reset.

b3: VPF: Vertical Polarity Flag

0=Positive, 1=Negative, Read Only, 0 after Reset.

b2: HPF: Horizontal Polarity Flag

0=Positive, 1=Negative, Read Only, 0 after Reset.

b1: VACQ:

Start

Vsync Period

Acquisition,

Read/Write, 0 after Reset (inverted in reading)

b0: SHH: Selection of Hsync or Hdrive as input

0=Hsync, 1=Hdrive, Write Only, 0 after Reset.

Event Counter Register 1 (ECR1)

Address: DDh - Read-Only

Reset Value: FFh

b7-b0: 8 LSB bits of counting result, Read Only,

FFh after Reset.

Event Counter2 And Clamp Control Register

(ECCCR)

Address: DEh - Read/Write

Reset Value: 0Fh

b7: COPC:

Clamp Output Polarity Control

0=positive - 1=negative

Write Only, 0 after Reset

b6: CMCT:

Clamp Control

0=CLMPO after HsyncO rising edge,

1=CLMPO after HsyncO falling edge,

Write Only, 0 after Reset.

b5-b4: CMW1, CMW0:

Clamp Pulse Width

Remark: CLMPO is forced to push-pull outputs.

Write Only, 0 after Reset

b3-b0: 4 MSB bits of Event Counting Result, Read

Only, XFh after Reset

Period Counter Register 1 (PCR1)

Address: DFh - Read-Only

Reset Value: FFh

b7-b0: 8 LSB bits of counting result, Read Only,

FFh after Reset.

HVOS HVGEN VOPC HOPC

VPF

HPF

VACQ

SHH

COPC

CMCT

CMW1 CMW0

H11

H10

CMW1

CMW0

Clamp Pulse

Width

Normal PA4

250 ns

500 ns

1000 ns

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