ST6373 datasheet(26/64 Pages) STMICROELECTRONICS

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ST6373

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INTERRUPTS (Cont’d)

Interrupt #1. The TIMER 3 Interrupt and the Port

A and B interrupts are connected by a logical AND

function to interrupt #1 (0FF6h). The TIMER 3 in-

terrupt generates a low level (which is latched in

the timer) requiring that the Interrupt 1 Edge/Level

bit is set to 1. The I/O Port A and B interrupts may

be set to generate an interrupt on the falling edge

or low level state of the input (EL1 = 1 or EL1 = 0

respectively) according to the external connec-

tions.Note that if a low level is maintained on an

I/O bit configured as acting on a Low Level after

the interrupt is generated, the MCU will return to

the interrupt state after exiting the RETI instruction

from the first interrupt service.

Interrupt #2. The VSYNC, Timer 2 and I2C SPI In-

terrupt are connected by a logical AND function to

interrupt #2. Bit 5 of the interrupt option register

C8h is used to select the negative edge (ES2=0)

or the positive edge (ES2=1) to trigger the inter-

rupt #2.For the correct operation of the Timer 2

and I

2C SPI interrupts, the falling edge should be

selected (ES2 = 0).For the VSYNC interrupt, either

edge can be selected, depending on the operation

required. For example if the rising edge on VSYNC

is the trigger, and after receiving the interrupt

edge, the VSYNC trigger level is switched to the

falling edge, the time between the rising and falling

edge (e.g. the display time) to be determined. The

VSYNC interrupt is controlled in Register NPVIR

at address EDh.

Note that once an edge has been latched, then the

only way to remove the latched signal is to service

the interrupt. Care must be taken not to generate

spurious interrupts. For example, changing the

edge selection bit from falling edge to rising edge

when the VSYNC input is high (or disabled in NP-

VIR) will cause a spurious interrupt.(see Interrupt

Circuit Diagram)

Interrupt #3. The TIMER 1 and DDC SPI Interrupt

are connected by a logical AND function to inter-

rupt #3. This interrupt is triggered on detection of a

low level latched in the timer and DDC SPI.

Interrupt #4. The PWRIN and Analog to Digital

Converter Interrupts are connected by a Logical

AND to interrupt #4 (0FF0h). The PWRIN interrupt

is controlled through the NPVIR Register at ad-

dress EDh, and the Phase Unlock interrupt is con-

trolled through SPCR at address DFh. The #4 in-

terrupt input detects a low level. A simple latch is

provided from the PC4 (PWRIN) pin in order to

generate the PWRINT signal. This latch can be

triggered by either the positive or negative edge of

the PWRIN signal (bit 3, PWREDGE, of register

NPVIR EDh). The latch is reset by software.

Notes:

Global disable does not reset edge sensitive inter-

rupt flags. These edge sensitive interrupts become

pending again when global disabling is released.

Moreover, edge sensitive interrupts are stored in

the related flags also when interrupts are globally

disabled, unless each edge sensitive interrupt is

also individually disabled before the interrupting

event happens. Global disable is done by clearing

the GEN bit of Interrupt option register, while any

individual disable is done in the control register of

the peripheral. The on-chip Timer peripherals

have an interrupt request flag bit (TMZ), this bit is

set to one when the device wants to generate an

interrupt request and a mask bit (ETI) that must be

set to one to allow the transfer of the flag bit to the

Core.

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