ST6373 datasheet(29/64 Pages) STMICROELECTRONICS

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ST6373

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4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

The ST6373 microcontroller uses three I/O ports

(A,B,C) with up to eight pins on each port. Each

line can be individually programmed either in the

input mode or the output mode with the following

software selectable options:

– Input without interrupt and without pull-up (Ports

A, B and C)

– Input with pull-up and with interrupt (PA0-PA5 and

Port B)

– Input with pull-up without interrupt (PA0-PA5 and

Port B, PC2-PC7)

– Analog Inputs (PB0-PB7)

– Open-drain output 12V, no pull-up (PC4-PC7)

– Open-drain output 5V (PA0-PA7, PB0-PB7,

PC0-PC3)

– Push-pull output (PA0-PA5, PB0-PB7)

– SPI control signals (PA6,PA7 for I2C SPI,

PC0,PC1,PC3 for DDC SPI)

–

Horizontal

Timing

inputs

(PC6/HSYNC,

PC7/HDRIV

– External Power In Interrupt (PC4)

The lines are organized in three ports (Ports A, B,

C). The ports occupy 8 registers in the data space.

Each bit of these registers is associated with a par-

ticular line (for instance, the bits 0 of the Port A Da-

ta, Direction and Option registers are associated

with the PA0 line of Port A).

The three Data registers (DRA, DRB, DRC) are

used to read the voltage level values of the lines

programmed in the input mode, or to write the logic

value of the signal to be output on the lines config-

ured in the output mode. The port Data Registers

can be read to get the effective logic levels of the

pins, but they can be also written by the user soft-

ware, in conjunction with the related Data Direc-

tion Register and Option Register (Ports A and B

only), to select the different input mode options.

Single-bit operations on I/O registers (bit set/reset

instructions) are possible but care is necessary

because reading in input mode is made from I/O

pins and therefore might be influenced by the ex-

ternal load, while writing will directly affect the Port

data register causing an undesired changes of the

input configuration.

The three Data Direction registers (DDRA, DDRB,

DDRC) allow the selection of the direction of each

pin (input or output).

The two Option registers (ORA and ORB) are used

to select the different port options available both in

input and in output mode for Ports A and B only.

All the I/O registers can be read or written as any

other RAM location of the data space, so no extra

RAM cell is needed for port data storing and ma-

nipulation. During the initialization of the MCU, all

the I/O registers are cleared and the input mode with

pull-up is selected on all the pins thus avoiding pin

conflicts (with the exception of PC2 which is set to

output mode with the value 1 (high impedance).

Figure 20. I/O Port Block Diagram (PA0-PA5 and Port B)

VA000413

RESET

INPUT/OUTPUT

DATA

DIRECTION

CONTROLS

DATA

TO INTERRUPT

OPTION

VDD

V DD

OUT

TO ADC

SHIFT

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