ST6373 datasheet(40/64 Pages) STMICROELECTRONICS

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ST6373

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4.4 SYNC PROCESSOR

This Sync Processor is composed of five parts:

– The first one is a 12 bits Event Counter with

HSYNC (or HDRIV) as input especially design to

calculate the HSYNC (respectively HDRIV) Fre-

quency.

– The second one is a 12-bits Period Counter es-

pecially designed to calculate the VSYNC period

and therefore his Frequency.

– The third one is a Polarity Detector for HSYNC

(or HDRIV) and VSYNC.

– The fourth part is a HSYNC,VSYNC and CLAMP

outputs generator.

– The last part is a Video Blanking generator.

4.4.1 Event Counter

The Counting is directly controlled by the Timer 3.

When PSI bit of Timer 3 Status Control Register is

low the Event Counter is in Reset Mode. At this

time the Timer 3 counter can be loaded by the

count period (for example 10 ms).

When PSI is set the Event Counter start simulta-

neously with the Timer.

When the timer count register has decremented to

zero the TMZ bit is set, an interrupt can be gener-

ated (if ETI bit is set) and the Event Counter stops.

The result number read inside the EVENT COUN-

TER REGISTERS corresponds to the rising edge

number of the Event Counter Clock occurred be-

tween the start and the stop. This Counter Clock is

set to one when the Counter is in reset (PSI=0) or

just stopped (after stop). It is equal to HSYNC

(HDRIV) between start and stop.

[If there is no HSYNC (HDRIV) the result inside the

counter will be: XFFFh]

Example: If the result is 5 the number of rising

edges is 6, the number of periods is: 4 < NP < 6).

Calculation: If the timer count is 10 ms the calcula-

tion of the HSYNC Frequency could be simple:

Freq. = N/10 KHz where N is the Event Counter re-

sult, the error is + or - one LSB max, it means 100

Hz. Of course the accuracy can be increased with

a higher timing count; 20 ms will give + or - 50 Hz.

4.4.2 Period Counter

The Vertical Period Counter is a 12-bits counter

with 8 us internal clock which measure by H/W the

duration between 2 VSYNC falling edges. Accura-

cy is 120+/-0.1 Hz. FVmin = 31 Hz. One measure-

ment start by setting the VACQuisition bit (write 1).

As this bit is inverted in reading, it is read at 1 after

Reset. As soon as the operation starts it is read at

0. At the end of the measurement,after the second

VSYNC Falling edge, the VACQuisition bit is read

again at 1.

Note: If FV < 31 Hz, VCOUNT = XFFFh = Max

If No V Sync, ACQ bit is not cleared

4.4.3 Polarity Detector

The VSYNC polarity detection is always active af-

ter reset so the software has only to read the Flag

(Bit 3 of SPCR) to determine the polarity. If the po-

larity of VSYNC changes, the Flag will switch after

a typical delay of 1.5 ms. The VSYNC polarity can

be read continuously.

The HSYNC/HDRIV polarity is returned in the Flag

(Bit 2 of SPCR). It is always running typically tog-

gles after one period of HSYNC/HDRIV when the

polarity changes.

The same delay has to be considered when

switching from HSYNC to HDRIV (Bit 0 of SPCR).

Refer to the VSYNC an HSYNC input Timings.

4.4.4 Output Polarity Control

The selection of HSYNCO instead of PA2 (respec-

tively VSYNCO instead of PA3) is made with the

bit 7 (HVOS) of SPCR.

HSYNCO and VSYNCO can take two different val-

ues according to the bit 6 (HVGEN) of SPCR:

- HSYNCI (respectively VSYNCI)

- HGEN: 62.5 KHz / Pulse width = 2us

(respectively VGEN: 61 Hz / Pulse width: 64 us).

The control of the HSYNCO and VSYNCO polarity

is made with respectively the bit 4 (HOPC) and bit

5 (VOPC) of SPCR.

The CLAMP output signal can be programmed af-

ter HSYNCO rising edge or HSYNCO falling edge

according to the bit 6 (CMCT) of ECCCR.

The CLAMP output polarity can be selected with

bit7 (COPC) of ECCCR.

The pulse width of CLMPO can have the values

250 ns, 500 ns or 1 ns according to the bits 5 and

4 (CMW1 and CMW0) of ECCCR.

Remark: when CMW1 = CMW0 = 0 PA4 is select-

ed.

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