ST6373 datasheet(23/64 Pages) STMICROELECTRONICS

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3.4 INTERRUPT

The MCU Core can manage 4 different maskable

interrupt sources, plus one non-maskable interrupt

source (top priority level interrupt). Each source is

associated with a particular interrupt vector that

contains a Jump instruction to the related interrupt

service routine. Each vector is located in the Pro-

gram Space at a particular address (see Table 7).

When a source provides an interrupt request, and

the request processing is also enabled by the

MCU Core, then the PC register is loaded with the

address of the interrupt vector (i.e. of the Jump in-

struction). Finally, the PC executes the Jump in-

struction and the interrupt routine is processed.

The relationship between vector and source and

the associated priority is hardware fixed for

ST6373 devices. For some interrupt sources it is

also possible to select by software the kind of

event that will generate the interrupt.

All interrupts can be disabled by writing to the GEN

bit (global interrupt enable) of the interrupt option

ST6373 is in non maskable interrupt mode, so no

interrupts will be accepted and NMI flags will be

used, until a RETI instruction is executed. If an in-

terrupt is executed, one special cycle is made by

the core, during that the PC is set to the related in-

terrupt vector address. A jump instruction at this

address has to redirect program execution to the

beginning of the related interrupt routine. The in-

terrupt detecting cycle, also resets the related in-

terrupt flag (not available to the user), so that an-

other interrupt can be stored for this current vector,

while its driver is under execution.

If additional interrupts arrive from the same

source, they will be lost. NMI can interrupt other in-

terrupt routines at any time, while other interrupts

cannot interrupt each other. If more than one inter-

rupt is waiting for service, they are executed ac-

cording to their priority. The lower the number, the

higher the priority. Priority is, therefore, fixed. In-

terrupts are checked during the last cycle of an in-

struction (RETI included). Level sensitive inter-

rupts have to be valid during this period.

Table

7 details

the different

interrupt

vec-

tors/sources relationships.

3.4.1 Interrupt Vectors/Sources

The MCU Core includes 5 different interrupt vec-

tors in order to branch to 5 different interrupt rou-

tines. The interrupt vectors are located in the fixed

(or static) page of the Program Space.

Table 7. Interrupt Vectors/Sources

Relationships

The interrupt vector associated with the non-

maskable interrupt source is named interrupt vec-

tor #0. It is located at the (FFCh, FFDh) addresses

in the Program Space. This vector is associated

with the NMI pin.

The

interrupt

vectors

located

addresses

(FF6h,FF7h),

(FF4h,FF5h),

(FF2h,FF3h),

(FF0h,FF1h) are named interrupt vectors #1, #2,

#3 and #4 respectively. These vectors are associ-

ated with TIMER 3, Port A and Port B interrupts

(#1), Timer 2, VSYNC and I

2C SPI (#2), TIMER 1

and the DDC SPI (#3) and the ADC and PC4

(PWRIN) (#4).

Interrupt Source

Associated

Vector

Address

NMI pin

Interrupt

Vector # 0 (NMI)

0FFCh-0FFDh

Timer 3

I/O Port A, I/O Port B

Interrupt

Vector # 1

0FF6h-0FF7h

Timer 2

VSYNC,

2C SPI

Interrupt

Vector #2

0FF4h-0FF5h

Timer 1

DDC SPI

Interrupt

Vector #3

0FF2h-0FF3h

ADC

PWRIN

Interrupt

Vector #4

0FF0h-0FF1h

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