ST6373 datasheet(21/64 Pages) STMICROELECTRONICS

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ST6373

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3.3 HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION

The hardware activated digital watchdog function

consists of a down counter that is automatically in-

itialized after reset so that this function does not

need to be activated by the user program. As the

watchdog function is always activated this down

counter can not be used as a timer. The watchdog

is using one data space register (HWDR location

D8h). The watchdog register is set to FEh on reset

and immediately starts to count down, requiring no

software start. Similarly the hardware activated

watchdog can not be stopped or delayed by soft-

ware.

The watchdog time can be programmed using the

6 MSBs in the watchdog register, this gives the

possibility to generate a reset in a time between

3072 to 196608 oscillator cycles in 64 possible

steps. (With a clock frequency of 8MHz this means

from 384ms to 24.576ms). The reset is prevented

if the register is reloaded with the desired value

before bits 2-7 decrement from all zeros to all

ones.

The presence of the hardware watchdog deacti-

vates the STOP instruction and a WAIT instruction

is automatically executed instead of a STOP. Bit 1

of the watchdog register (set to one at reset) can

be used to generate a software reset if cleared to

zero). Figure 1 shows the watchdog block diagram

while Figure 2 shows its working principle.

Figure 16. Hardware Activated Watchdog Block Diagram

RSFF

DATA BUS

VA00010

-2

-12

OSCILLATOR

RESET

WRITE

RESET

DB0

DB1.7

SE T

LOAD

-2

SET

CLOCK

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