ST6373 datasheet(12/64 Pages) STMICROELECTRONICS

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ST6373

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MEMORY SPACES (Cont’d)

1.3.4 Data RAM/EEPROM

In the ST6373, 64 bytes of data RAM are directly

addressable in the data space from 80h to BFh ad-

dresses. The additional 128 bytes of RAM, and the

384 + 128 bytes of EEPROM can be addressed

using the 64-byte banks located between address-

es 00H and 3Fh. Bank selection is carried out by

programming the Data RAM Bank Register (DR-

BR) located at address E8h of the Data Space. In

this way each bank of RAM or EEPROM can se-

lect 64 bytes at a time. No more than one bank

should be set at a time.

Data RAM Bank Register (DRBR)

Address: E8h - Write only

Reset Value: XXh

DRBR6. This bit is reserved and must be held at

“0”.

DRBR5, DRBR4. Each of these bits, when set, will

select one page of the EEPROM dedicated to the

DDC SPI.

DRBR3, DRBR2. Each of these bits, when set, will

select oneRAM page.

DRBR7, DRBR1, DRBR0. These bits select the

EEPROM pages.

This register is undefined after reset.

Table 5 summarizes how to set the Data RAM

Bank Register in order to select the various banks

or pages.

Note:

Care is required when handling the DRBR as it is

write only. For this reason, it is not allowed to

change the DRBR contents while executing inter-

rupts drivers, as the driver cannot save and than

restore its previous content. If it is impossible to

avoid the writing of this register in interrupts driv-

ers, an image of this register must be saved in a

RAM location, and each time the program writes

the DRBR it writes also the image register. The im-

age register must be written first, so if an interrupt

occurs between the two instructions the DRBR is

not affected.

1.3.5 EEPROM Description

The data space of ST6373 devices, from 00h to

3Fh, is paged as described in Table 5. The 512

bytes of EEPROM are located in eight pages of 64

bytes (see Table 3 below).

Table 5. Data RAM Bank Register Set-up

DRBR

DRBR Value

Selection

Hex.

Binary

01h

0000 0001

EEPROM Page 0

02h

0000 0010

EEPROM Page 1

03h

0000 0011

EEPROM Page 2

04h

0000 0100

RAM Page 2

08h

0000 1000

RAM Page 3

10h

0001 0000

DDC EEPROM Page 0

20h

0010 0000

DDC EEPROM Page 1

81h

1000 0001

EEPROM Page 3

82h

1000 0010

EEPROM Page 4

83h

1000 0011

EEPROM Page 5

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